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-rw-r--r--src/soc/intel/braswell/chip.h3
-rw-r--r--src/soc/intel/braswell/include/soc/romstage.h4
2 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index bb06dd595a..5a00328f4d 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -32,9 +32,6 @@
#define SVID_CONFIG3 3
#define SVID_PMIC_CONFIG 8
-#define MEM_DDR3 0
-#define MEM_LPDDR3 1
-
enum lpe_clk_src {
LPE_CLK_SRC_XTAL,
LPE_CLK_SRC_PLL,
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 8fa9c8a713..2512430f75 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -34,4 +34,8 @@ void set_max_freq(void);
void program_base_addresses(void);
int chipset_prev_sleep_state(struct chipset_power_state *ps);
+/* Values for FSP's PcdMemoryTypeEnable */
+#define MEM_DDR3 0
+#define MEM_LPDDR3 1
+
#endif /* _SOC_ROMSTAGE_H_ */