diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/nvs.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/uart.c | 24 | ||||
| -rw-r--r-- | src/soc/intel/common/block/smm/smihandler.c | 3 |
5 files changed, 30 insertions, 4 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 07bbdcdc65..589b846012 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -42,6 +42,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += spi.c smm-y += uart_early.c +smm-y += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 1548c305eb..6431faee4a 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -41,6 +41,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PRT0, 32, // 0x25 - 0x28 - PERST_0 Address SCDP, 8, // 0x29 - SD_CD GPIO portid SCDO, 8, // 0x2A - GPIO pad offset relative to the community + UIOR, 8, // 0x2B - UART debug controller init on S3 resume + /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 56085b25a6..9a098003c4 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -42,7 +42,9 @@ typedef struct global_nvs_t { uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ uint8_t scdp; /* 0x29 - SD_CD GPIO portid */ uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */ - uint8_t unused[213]; + uint8_t uior; /* 0x2B - UART debug controller init on S3 + resume */ + uint8_t unused[212]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 3db460a999..673039cbe8 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -20,20 +20,38 @@ * shouldn't cause any fragmentation. */ +#include <cbmem.h> #include <device/device.h> #include <device/pci.h> #include <intelblocks/uart.h> +#include <soc/nvs.h> #include <soc/pci_devs.h> +#if !ENV_SMM void pch_uart_read_resources(struct device *dev) { pci_dev_read_resources(dev); - if ((IS_ENABLED(CONFIG_SOC_UART_DEBUG) && - dev->path.pci.devfn == _PCH_DEVFN(UART, - CONFIG_UART_FOR_CONSOLE))) { + if (IS_ENABLED(CONFIG_SOC_UART_DEBUG) && + uart_is_debug_controller(dev)) { /* will override existing resource. */ fixed_mem_resource(dev, PCI_BASE_ADDRESS_0, CONFIG_CONSOLE_UART_BASE_ADDRESS >> 10, 4, 0); } } +#endif + +bool pch_uart_init_debug_controller_on_resume(void) +{ + global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) + return !!gnvs->uior; + + return false; +} + +device_t pch_uart_get_debug_controller(void) +{ + return _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE); +} diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 24327f2aa8..3f1f490861 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -23,6 +23,7 @@ #include <elog.h> #include <intelblocks/pmclib.h> #include <intelblocks/smihandler.h> +#include <intelblocks/uart.h> #include <soc/nvs.h> #include <soc/pm.h> #include <soc/gpio.h> @@ -161,6 +162,8 @@ void smihandler_southbridge_sleep( case ACPI_S3: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + gnvs->uior = uart_debug_controller_is_initialized(); + /* Invalidate the cache before going to S3 */ wbinvd(); break; |