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-rw-r--r--src/soc/amd/cezanne/Kconfig8
-rw-r--r--src/soc/amd/cezanne/Makefile.inc4
-rw-r--r--src/soc/amd/cezanne/fsp_params.c7
-rw-r--r--src/soc/amd/cezanne/romstage.c5
4 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index ecdba5e6a6..15a40377cd 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -16,6 +16,7 @@ config SOC_SPECIFIC_OPTIONS
select HAVE_CF9_RESET
select IDT_IN_EVERY_STAGE
select IOAPIC
+ select PLATFORM_USES_FSP2_0
select RESET_VECTOR_IN_RAM
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
@@ -27,6 +28,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_UART
+ select UDK_2017_BINDING
config CHIPSET_DEVICETREE
string
@@ -92,6 +94,12 @@ config FSP_M_SIZE
help
Sets the size of DRAM allocation for FSP-M in linker script.
+config FSP_TEMP_RAM_SIZE
+ hex
+ default 0x40000
+ help
+ The amount of coreboot-allocated heap and stack usage by the FSP.
+
config RAMBASE
hex
default 0x10000000
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index a00a9f575c..46ac199649 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -25,11 +25,15 @@ romstage-y += romstage.c
romstage-y += uart.c
ramstage-y += chip.c
+ramstage-y += fsp_params.c
ramstage-y += gpio.c
ramstage-y += reset.c
ramstage-y += uart.c
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
+CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne
+
+$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR)
MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)
diff --git a/src/soc/amd/cezanne/fsp_params.c b/src/soc/amd/cezanne/fsp_params.c
new file mode 100644
index 0000000000..d3f9fcf555
--- /dev/null
+++ b/src/soc/amd/cezanne/fsp_params.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+}
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 91074b2012..52ff0f8e41 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -1,6 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/cpu.h>
+#include <fsp/api.h>
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+}
asmlinkage void car_stage_entry(void)
{