diff options
Diffstat (limited to 'src/soc')
29 files changed, 93 insertions, 93 deletions
diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index 23f6471689..91c591e345 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -58,5 +58,5 @@ static void bootblock_mmu_init(void) C0_ENTRYLO_COHERENCY_WB)); assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB)); assert(!identity_map((uint32_t)_soc_registers, _soc_registers_size, - C0_ENTRYLO_COHERENCY_UC)); + C0_ENTRYLO_COHERENCY_UC)); } diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index bf93ef40a8..9226ac3bd1 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -174,7 +174,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; } - cfg = dev->chip_info; + cfg = dev->chip_info; if(cfg->lpss_s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 4ea89710ab..ba10e35562 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -573,7 +573,7 @@ static void glk_fsp_silicon_init_params_cb( void __weak mainboard_devtree_update(struct device *dev) { - /* Override dev tree settings per board */ + /* Override dev tree settings per board */ } void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c index a46b188a95..6a71f1ee7e 100644 --- a/src/soc/intel/apollolake/nhlt.c +++ b/src/soc/intel/apollolake/nhlt.c @@ -260,7 +260,7 @@ int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink) int nhlt_soc_add_rt5682(struct nhlt *nhlt, int hwlink) { - /* Virtual bus id of SSP links are the hardware port ids proper. */ - return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5682_descriptors, - ARRAY_SIZE(rt5682_descriptors)); + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5682_descriptors, + ARRAY_SIZE(rt5682_descriptors)); } diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 5da510486b..451993df2f 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -170,7 +170,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios, } static void setup_gpio_route(const struct soc_gpio_map *sus, - const struct soc_gpio_map *core) + const struct soc_gpio_map *core) { uint32_t route_reg = 0; int i; diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 30e6d1d94b..51c3ea065b 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -52,7 +52,7 @@ uint16_t get_pmbase(void) } static void print_num_status_bits(int num_bits, uint32_t status, - const char *bit_names[]) + const char *bit_names[]) { int i; diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 027e0d8edc..07b801093f 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -97,8 +97,8 @@ static void spi_init(void) } /* Entry from cache-as-ram.inc. */ -void *asmlinkage romstage_main(unsigned long bist, - uint32_t tsc_low, uint32_t tsc_hi) +void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, + uint32_t tsc_hi) { struct romstage_params rp = { .bist = bist, diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c index 0f47173061..300556a45f 100644 --- a/src/soc/intel/cannonlake/cbmem.c +++ b/src/soc/intel/cannonlake/cbmem.c @@ -17,6 +17,6 @@ void *cbmem_top(void) { - /* not implemented yet */ + /* not implemented yet */ return (void *) NULL; } diff --git a/src/soc/intel/cannonlake/nhlt.c b/src/soc/intel/cannonlake/nhlt.c index ff1b4464ba..ca31d39574 100644 --- a/src/soc/intel/cannonlake/nhlt.c +++ b/src/soc/intel/cannonlake/nhlt.c @@ -231,7 +231,7 @@ static const struct nhlt_endp_descriptor max98373_descriptors[] = { .did = NHLT_DID_SSP, .formats = max98373_capture_formats, .num_formats = ARRAY_SIZE(max98373_capture_formats), - }, + }, }; int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 45ee940849..225914c5b5 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -155,8 +155,8 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count) if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) dpr_size = sa_get_dpr_size(); - /* Get SoC reserve memory size as per user selection */ - reserved_mmio_size = soc_reserved_mmio_size(); + /* Get SoC reserve memory size as per user selection */ + reserved_mmio_size = soc_reserved_mmio_size(); top_of_ram = (uintptr_t)cbmem_top(); diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 72cf158b21..72ba517d52 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -186,7 +186,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios, } static void setup_gpio_route(const struct soc_gpio_map *sus, - const struct soc_gpio_map *core) + const struct soc_gpio_map *core) { uint32_t route_reg = 0; int i; @@ -319,7 +319,7 @@ void write_ssus_gpio(uint8_t gpio_num, uint8_t val) * pad value: PAD_VAL_HIGH / PAD_VAL_LOW */ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num, - uint32_t pconf0, uint32_t pad_val) + uint32_t pconf0, uint32_t pad_val) { uint32_t reg; uint32_t *pad_addr; diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index f99b7c3fc7..9798798504 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -266,34 +266,34 @@ Device (TSR1) #ifdef DPTF_ENABLE_FAN_CONTROL #ifdef DPTF_TSR1_ACTIVE_AC0 - Method (_AC0) - { - Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0)) - } + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0)) + } #endif #ifdef DPTF_TSR1_ACTIVE_AC1 - Method (_AC1) - { - Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1)) - } + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1)) + } #endif #ifdef DPTF_TSR1_ACTIVE_AC2 - Method (_AC2) - { - Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2)) - } + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2)) + } #endif #ifdef DPTF_TSR1_ACTIVE_AC3 - Method (_AC3) - { - Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3)) - } + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3)) + } #endif #ifdef DPTF_TSR1_ACTIVE_AC4 - Method (_AC4) - { - Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4)) - } + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4)) + } #endif #endif } diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 29367de6dd..a23d78abd9 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -195,8 +195,8 @@ Device (XHCI) Store (3, ^UPSW) /* Enable d3hot and SS link trunk clock gating */ - Store(One, ^D3HE) - Store(One, ^STGE) + Store(One, ^D3HE) + Store(One, ^STGE) /* Now put device in D3 */ Store (3, Local0) diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index beb455874f..0e3a4130b1 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -75,7 +75,7 @@ static const struct nhlt_endp_descriptor max98373_descriptors[] = { .did = NHLT_DID_SSP, .formats = max98373_capture_formats, .num_formats = ARRAY_SIZE(max98373_capture_formats), - }, + }, }; int nhlt_soc_add_max98373(struct nhlt *nhlt, int hwlink) diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 4babd542f6..b5826579ba 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -39,7 +39,7 @@ inline u8 is_dual_rank(u32 channel, const struct mt8173_sdram_params *sdram_params) { /* judge ranks from EMI_CONA[17] (cha) and EMI_CONA[16] (chb) */ - return (sdram_params->emi_set.cona & (1 << (17 - channel))) ? 1 : 0; + return (sdram_params->emi_set.cona & (1 << (17 - channel))) ? 1 : 0; } static void mem_pll_pre_init(u32 channel) diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 8ed82b119f..7a25bfe8a7 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -343,7 +343,7 @@ static u8 dqs_gw_coarse_tune_calib(u32 channel, u8 coarse_val) gw_ret[i] = dqs_gw_test(channel); /* judge test result */ if (gw_ret[i] != 0) - return opt_coarse_val[i]; + return opt_coarse_val[i]; } /* abnormal test result, set to default coarse tune value */ @@ -747,7 +747,7 @@ u8 rx_datlat_cal(u32 channel, u8 rank, } /* Default dle value is set when test error (error recovery). - * Others, adjusted dle calibration value is set normally. + * Others, adjusted dle calibration value is set normally. */ set_dle_factor(channel, best_step); diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 4f6ba32622..ecea693f4f 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -86,7 +86,7 @@ static void mt6391_configure_vcama(enum ldo_voltage vsel) mt6391_write(PMIC_RG_ANALDO_CON6, vsel - 2, PMIC_RG_VCAMA_VOSEL_MASK, PMIC_RG_VCAMA_VOSEL_SHIFT); mt6391_write(PMIC_RG_ANALDO_CON2, 1, PMIC_RG_VCAMA_EN_MASK, - PMIC_RG_VCAMA_EN_SHIFT); + PMIC_RG_VCAMA_EN_SHIFT); } void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel) diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 7d3e0bff90..4db7808a80 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -212,7 +212,7 @@ void i2c_init(unsigned bus) struct tegra_i2c_regs *regs; if (bus >= g_num_i2c_buses) { - printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__, + printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__, bus); return; } diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index d9ab67bf5f..7e930d11d6 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -75,7 +75,7 @@ struct soc_nvidia_tegra124_config { int hpd_unplug_min_us; int hpd_plug_min_us; - int hpd_irq_min_us; + int hpd_irq_min_us; int href_to_sync; int hsync_width; diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index febb420497..c90e392e0e 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -40,26 +40,26 @@ struct tegra_dc dc_data; int dump = 0; unsigned long READL(void *p) { - unsigned long value; + unsigned long value; /* * In case of hard hung on readl(p), we can set dump > 1 to print out * the address accessed. */ - if (dump > 1) + if (dump > 1) printk(BIOS_SPEW, "readl %p\n", p); - value = read32(p); - if (dump) + value = read32(p); + if (dump) printk(BIOS_SPEW, "readl %p %08lx\n", p, value); - return value; + return value; } void WRITEL(unsigned long value, void *p) { - if (dump) + if (dump) printk(BIOS_SPEW, "writel %p %08lx\n", p, value); - write32(p, value); + write32(p, value); } /* return in 1000ths of a Hertz */ diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index a9b8d7da97..7fae4e9a45 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -1362,10 +1362,10 @@ void dp_init(void *_config) struct tegra_dc *dc = config->dc_data; struct tegra_dc_dp_data *dp = &dp_data; - // set up links among config, dc, dp and sor - dp->dc = dc; - dc->out = dp; - dp->sor.dc = dc; + // set up links among config, dc, dp and sor + dp->dc = dc; + dc->out = dp; + dp->sor.dc = dc; dp->sor.power_is_up = 0; dp->sor.base = (void *)TEGRA_ARM_SOR; @@ -1427,7 +1427,7 @@ void dp_enable(void *_dp) if (tegra_dc_dp_init_max_link_cfg(config, dp, &dp->link_cfg)) { printk(BIOS_ERR, "dp: failed to init link configuration\n"); goto error_enable; - } + } tegra_dc_sor_enable_dp(&dp->sor); diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index b892c602b3..10003463c0 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -25,26 +25,26 @@ int dump = 0; unsigned long READL(void *p) { - unsigned long value; + unsigned long value; /* * In case of hard hung on readl(p), we can set dump > 1 to print out * the address accessed. */ - if (dump > 1) + if (dump > 1) printk(BIOS_SPEW, "readl %p\n", p); - value = read32(p); - if (dump) + value = read32(p); + if (dump) printk(BIOS_SPEW, "readl %p %08lx\n", p, value); - return value; + return value; } void WRITEL(unsigned long value, void *p) { - if (dump) + if (dump) printk(BIOS_SPEW, "writel %p %08lx\n", p, value); - write32(p, value); + write32(p, value); } /* return in 1000ths of a Hertz */ @@ -76,7 +76,7 @@ static void print_mode(const struct soc_nvidia_tegra210_config *config) } int update_display_mode(struct display_controller *disp_ctrl, - struct soc_nvidia_tegra210_config *config) + struct soc_nvidia_tegra210_config *config) { print_mode(config); @@ -124,7 +124,7 @@ int update_display_mode(struct display_controller *disp_ctrl, } void update_display_shift_clock_divider(struct display_controller *disp_ctrl, - u32 shift_clock_div) + u32 shift_clock_div) { WRITEL((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) | (shift_clock_div & 0xff) << SHIFT_CLK_DIVIDER_SHIFT, diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 532ffc3122..205bc1e1db 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -886,12 +886,12 @@ static int dsi_probe_if(int dsi_index, /* * Set default value. Will be taken from attached device once detected */ - dsi->flags = 0; - dsi->format = MIPI_DSI_FMT_RGB888; - dsi->lanes = 4; + dsi->flags = 0; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->lanes = 4; /* get tegra_mipi_device */ - dsi->mipi = tegra_mipi_request(&mipi_device_data[dsi_index], dsi_index); + dsi->mipi = tegra_mipi_request(&mipi_device_data[dsi_index], dsi_index); /* calibrate */ err = tegra_dsi_pad_calibrate(dsi); diff --git a/src/soc/nvidia/tegra210/romstage_asm.S b/src/soc/nvidia/tegra210/romstage_asm.S index 9bceadb6fc..110149b0d9 100644 --- a/src/soc/nvidia/tegra210/romstage_asm.S +++ b/src/soc/nvidia/tegra210/romstage_asm.S @@ -16,7 +16,7 @@ #include <arch/asm.h> #include "stack.S" - .section ".text", "ax", %progbits + .section ".text", "ax", %progbits ENTRY(main) stack_init stack_top=_estack stack_bottom=_stack seed=0 func=romstage diff --git a/src/soc/nvidia/tegra210/stack.S b/src/soc/nvidia/tegra210/stack.S index acab70c9ec..416cdb39f9 100644 --- a/src/soc/nvidia/tegra210/stack.S +++ b/src/soc/nvidia/tegra210/stack.S @@ -21,7 +21,7 @@ * @func : Function to call after initializing stack */ .macro stack_init stack_top, stack_bottom, seed, func - /* Check if stack seeding is required */ + /* Check if stack seeding is required */ mov r0, #\seed cmp r0, #1 bne call_func diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 4498b31183..d47b9c5995 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -657,7 +657,7 @@ static int spi_ctrlr_setup(const struct spi_slave *slave) || ((bus == BLSP1_SPI) && (cs > 0))) { printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) " - "or chipselect\n", bus); + "or chipselect\n", bus); return -1; } diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index 35a3283bce..15e9e6fbc8 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -63,17 +63,17 @@ void gpio_tlmm_config_set(gpio_t gpio, unsigned func, unsigned pull, unsigned drvstr, unsigned enable) { - unsigned val = 0; + unsigned val = 0; if (gpio_not_valid(gpio)) return; - val |= (pull & GPIO_CFG_PULL_MASK) << GPIO_CFG_PULL_SHIFT; - val |= (func & GPIO_CFG_FUNC_MASK) << GPIO_CFG_FUNC_SHIFT; - val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT; - val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT; + val |= (pull & GPIO_CFG_PULL_MASK) << GPIO_CFG_PULL_SHIFT; + val |= (func & GPIO_CFG_FUNC_MASK) << GPIO_CFG_FUNC_SHIFT; + val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT; + val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT; - write32(GPIO_CONFIG_ADDR(gpio), val); + write32(GPIO_CONFIG_ADDR(gpio), val); } /******************************************************* @@ -93,8 +93,8 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned *func, unsigned *pull, unsigned *drvstr, unsigned *enable) { - unsigned val; - void *addr = GPIO_CONFIG_ADDR(gpio); + unsigned val; + void *addr = GPIO_CONFIG_ADDR(gpio); if (gpio_not_valid(gpio)) return; diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c index ea4778b931..295ef399c2 100644 --- a/src/soc/samsung/exynos5420/clock_init.c +++ b/src/soc/samsung/exynos5420/clock_init.c @@ -41,7 +41,7 @@ void system_clock_init(void) write32(&exynos_clock->ipll_lock, IPLL_LOCK_VAL); write32(&exynos_clock->spll_lock, SPLL_LOCK_VAL); write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL); - write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL); + write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL); setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK); @@ -138,7 +138,7 @@ void system_clock_init(void) while ((read32(&exynos_clock->spll_con0) & PLL_LOCKED) == 0) ; - /* We use RPLL as the source for FIMD video stream clock */ + /* We use RPLL as the source for FIMD video stream clock */ write32(&exynos_clock->rpll_con1, RPLL_CON1_VAL); write32(&exynos_clock->rpll_con2, RPLL_CON2_VAL); /* computed by gabe from first principles; u-boot is probably diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index a7adf9347c..aa850bcb81 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -304,16 +304,16 @@ void exynos_fimd_window_off(unsigned int win_id) static void exynos5_set_system_display(void) { - unsigned int cfg = 0; - - /* - * system register path set - * 0: MIE/MDNIE - * 1: FIMD Bypass - */ - cfg = lreadl(&exynos_sysreg->disp1blk_cfg); - cfg |= (1 << 15); - lwritel(cfg, &exynos_sysreg->disp1blk_cfg); + unsigned int cfg = 0; + + /* + * system register path set + * 0: MIE/MDNIE + * 1: FIMD Bypass + */ + cfg = lreadl(&exynos_sysreg->disp1blk_cfg); + cfg |= (1 << 15); + lwritel(cfg, &exynos_sysreg->disp1blk_cfg); } void exynos_fimd_lcd_init(vidinfo_t *vid) |