diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/smbus.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/smbus.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/smbus.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/smbus/smbus.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/smbus.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/icelake/include/soc/smbus.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/smbus.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/smbus.h | 2 |
8 files changed, 3 insertions, 20 deletions
diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/soc/intel/broadwell/include/soc/smbus.h index 40aaf438a8..ed37373360 100644 --- a/src/soc/intel/broadwell/include/soc/smbus.h +++ b/src/soc/intel/broadwell/include/soc/smbus.h @@ -22,7 +22,6 @@ #define SMB_BASE 0x20 #define HOSTC 0x40 #define HST_EN (1 << 0) -#define SMB_RCV_SLVA 0x09 /* SMBus I/O bits. */ #define SMBHSTSTAT 0x0 diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index c32e31d6a9..0ac2ffc388 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -24,7 +24,6 @@ #include <soc/iomap.h> #include <soc/ramstage.h> #include <soc/smbus.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> static void pch_smbus_init(struct device *dev) @@ -40,7 +39,7 @@ static void pch_smbus_init(struct device *dev) /* Set Receive Slave Address */ res = find_resource(dev, PCI_BASE_ADDRESS_4); if (res) - outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); + smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } static int lsmbus_read_byte(struct device *dev, u8 address) diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h index e3d93a2a54..54d0d6cfbf 100644 --- a/src/soc/intel/cannonlake/include/soc/smbus.h +++ b/src/soc/intel/cannonlake/include/soc/smbus.h @@ -19,10 +19,6 @@ #ifndef _SOC_CANNONLAKE_SMBUS_H_ #define _SOC_CANNONLAKE_SMBUS_H_ -/* IO and MMIO registers under primary BAR */ -/* Set address for PCH as SMBus slave role */ -#define SMB_RCV_SLVA 0x09 - /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index ce75f3a891..a99efafe85 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -13,14 +13,12 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/device.h> #include <device/path.h> #include <device/smbus.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/smbus.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "smbuslib.h" @@ -63,7 +61,7 @@ static void pch_smbus_init(struct device *dev) /* Set Receive Slave Address */ res = find_resource(dev, PCI_BASE_ADDRESS_4); if (res) - outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); + smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } static void smbus_read_resources(struct device *dev) diff --git a/src/soc/intel/denverton_ns/include/soc/smbus.h b/src/soc/intel/denverton_ns/include/soc/smbus.h index 5dbeecc0cf..5668440af3 100644 --- a/src/soc/intel/denverton_ns/include/soc/smbus.h +++ b/src/soc/intel/denverton_ns/include/soc/smbus.h @@ -25,7 +25,7 @@ #define HST_EN (1 << 0) #define HOSTC_SMI_EN (1 << 1) #define HOSTC_I2C_EN (1 << 2) -#define SMB_RCV_SLVA 0x09 + /* SMBUS TCO base address. */ #define TCOBASE 0x50 #define MASK_TCOBASE 0xffe0 diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h index f4f5b11288..9d8fe46b64 100644 --- a/src/soc/intel/icelake/include/soc/smbus.h +++ b/src/soc/intel/icelake/include/soc/smbus.h @@ -16,10 +16,6 @@ #ifndef _SOC_ICELAKE_SMBUS_H_ #define _SOC_ICELAKE_SMBUS_H_ -/* IO and MMIO registers under primary BAR */ -/* Set address for PCH as SMBus slave role */ -#define SMB_RCV_SLVA 0x09 - /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index aad57aabb6..ee257ea613 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -19,9 +19,6 @@ #ifndef _SOC_SMBUS_H_ #define _SOC_SMBUS_H_ -/* PCI Configuration Space (D31:F3): SMBus */ -#define SMB_RCV_SLVA 0x09 - /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h index 9226fba4e1..50ea044e53 100644 --- a/src/soc/intel/tigerlake/include/soc/smbus.h +++ b/src/soc/intel/tigerlake/include/soc/smbus.h @@ -23,8 +23,6 @@ #define _SOC_TIGERLAKE_SMBUS_H_ /* IO and MMIO registers under primary BAR */ -/* Set address for PCH as SMBus slave role */ -#define SMB_RCV_SLVA 0x09 /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 |