6 files changed, 34 insertions, 64 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 4afe47cbff..5bde819ec6 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -205,34 +205,3 @@ void cpx_init_cpus(struct device *dev)
 	/* update numa domain for all cpu devices */
 	xeonsp_init_cpu_config();
 }
-
-msr_t read_msr_ppin(void)
-{
-	msr_t ppin = {0};
-	msr_t msr;
-
-	/* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
-	msr = rdmsr(MSR_PLATFORM_INFO);
-	if ((msr.lo & MSR_PPIN_CAP) == 0) {
-		printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
-		return ppin;
-	}
-
-	/* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
-	msr = rdmsr(MSR_PPIN_CTL);
-	if (msr.lo & MSR_PPIN_CTL_LOCK) {
-		printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
-		return ppin;
-	}
-
-	if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
-		/* Set MSR_PPIN_CTL ENABLE to 1 */
-		msr.lo |= MSR_PPIN_CTL_ENABLE;
-		wrmsr(MSR_PPIN_CTL, msr);
-	}
-	ppin = rdmsr(MSR_PPIN);
-	/* Set enable to 0 after reading MSR_PPIN */
-	msr.lo &= ~MSR_PPIN_CTL_ENABLE;
-	wrmsr(MSR_PPIN_CTL, msr);
-	return ppin;
-}
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
index 19f6e4c5d5..693de8fbcc 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
@@ -10,6 +10,5 @@
 #define CPUID_COOPERLAKE_SP_A1			0x05065b
 
 void cpx_init_cpus(struct device *dev);
-msr_t read_msr_ppin(void);
 
 #endif
diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h
index 8c2b597247..51e2b69b00 100644
--- a/src/soc/intel/xeon_sp/include/soc/util.h
+++ b/src/soc/intel/xeon_sp/include/soc/util.h
@@ -3,10 +3,12 @@
 #ifndef _XEON_SP_SOC_UTIL_H_
 #define _XEON_SP_SOC_UTIL_H_
 
+#include <cpu/x86/msr.h>
 #include <hob_iiouds.h>
 
 void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3);
 void unlock_pam_regions(void);
 void get_stack_busnos(uint32_t *bus);
+msr_t read_msr_ppin(void);
 
 #endif
diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index 581378b410..874bcfd6d7 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -245,34 +245,3 @@ void xeon_sp_init_cpus(struct device *dev)
 
 	FUNC_EXIT();
 }
-
-msr_t read_msr_ppin(void)
-{
-	msr_t ppin = {0};
-	msr_t msr;
-
-	/* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
-	msr = rdmsr(MSR_PLATFORM_INFO);
-	if ((msr.lo & MSR_PPIN_CAP) == 0) {
-		printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
-		return ppin;
-	}
-
-	/* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
-	msr = rdmsr(MSR_PPIN_CTL);
-	if (msr.lo & MSR_PPIN_CTL_LOCK) {
-		printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
-		return ppin;
-	}
-
-	if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
-		/* Set MSR_PPIN_CTL ENABLE to 1 */
-		msr.lo |= MSR_PPIN_CTL_ENABLE;
-		wrmsr(MSR_PPIN_CTL, msr);
-	}
-	ppin = rdmsr(MSR_PPIN);
-	/* Set enable to 0 after reading MSR_PPIN */
-	msr.lo &= ~MSR_PPIN_CTL_ENABLE;
-	wrmsr(MSR_PPIN_CTL, msr);
-	return ppin;
-}
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h
index c2af265b91..0e3028da74 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h
@@ -16,6 +16,5 @@
 
 int get_cpu_count(void);
 void xeon_sp_init_cpus(struct device *dev);
-msr_t read_msr_ppin(void);
 
 #endif
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index 77fc1e4941..66b9ef11c1 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -3,6 +3,7 @@
 #include <console/console.h>
 #include <device/pci.h>
 #include <soc/pci_devs.h>
+#include <soc/msr.h>
 #include <soc/util.h>
 
 void get_stack_busnos(uint32_t *bus)
@@ -53,3 +54,34 @@ void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus
 	if (bus3)
 		*bus3 = (bus >> 24) & 0xff;
 }
+
+msr_t read_msr_ppin(void)
+{
+	msr_t ppin = {0};
+	msr_t msr;
+
+	/* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if ((msr.lo & MSR_PPIN_CAP) == 0) {
+		printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
+		return ppin;
+	}
+
+	/* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
+	msr = rdmsr(MSR_PPIN_CTL);
+	if (msr.lo & MSR_PPIN_CTL_LOCK) {
+		printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
+		return ppin;
+	}
+
+	if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
+		/* Set MSR_PPIN_CTL ENABLE to 1 */
+		msr.lo |= MSR_PPIN_CTL_ENABLE;
+		wrmsr(MSR_PPIN_CTL, msr);
+	}
+	ppin = rdmsr(MSR_PPIN);
+	/* Set enable to 0 after reading MSR_PPIN */
+	msr.lo &= ~MSR_PPIN_CTL_ENABLE;
+	wrmsr(MSR_PPIN_CTL, msr);
+	return ppin;
+}