diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/skylake/pmc.c | 17 |
3 files changed, 17 insertions, 11 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index b3b999f53c..a75f5260a5 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -610,7 +610,8 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) * Chipset state in the suspend well (but not RTC) is lost in Deep S3 * so enable Deep S3 wake events that are configured by the mainboard */ - if (ps->prev_sleep_state == ACPI_S3 && config->deep_s3_enable) { + if (ps->prev_sleep_state == ACPI_S3 && + (config->deep_s3_enable_ac || config->deep_s3_enable_dc)) { pm1_en |= PWRBTN_STS; /* Always enabled as wake source */ if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN) gpe0_std |= LAN_WAK_EN; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index ce5fe22b98..cd461d4430 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -86,9 +86,11 @@ struct soc_intel_skylake_config { /* Enable DPTF support */ int dptf_enable; - /* Deep SX enable for both AC and DC */ - int deep_s3_enable; - int deep_s5_enable; + /* Deep SX enables */ + int deep_s3_enable_ac; + int deep_s3_enable_dc; + int deep_s5_enable_ac; + int deep_s5_enable_dc; /* * Deep Sx Configuration diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 64df18650b..f3a2681dd5 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -189,16 +189,19 @@ static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) write32(pmcbase + offset, reg); } -static void config_deep_s5(int on) +static void config_deep_s5(int on_ac, int on_dc) { /* Treat S4 the same as S5. */ - config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS | S4AC_GATE_SUS, 4, on); - config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS | S5AC_GATE_SUS, 5, on); + config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); + config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); + config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); + config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); } -static void config_deep_s3(int on) +static void config_deep_s3(int on_ac, int on_dc) { - config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS | S3AC_GATE_SUS, 3, on); + config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); + config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); } static void config_deep_sx(uint32_t deepsx_config) @@ -226,8 +229,8 @@ static void pmc_init(struct device *dev) reg_script_run_on_dev(dev, pch_pmc_misc_init_script); pch_set_acpi_mode(); - config_deep_s3(config->deep_s3_enable); - config_deep_s5(config->deep_s5_enable); + config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); + config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); config_deep_sx(config->deep_sx_config); /* Clear registers that contain write-1-to-clear bits. */ |