diff options
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/intel/pantherlake/Makefile.mk | 4 | ||||
-rw-r--r-- | src/soc/intel/pantherlake/cpu.c | 1 | ||||
-rw-r--r-- | src/soc/intel/pantherlake/elog.c | 6 | ||||
-rw-r--r-- | src/soc/intel/pantherlake/include/soc/soc_info.h | 16 | ||||
-rw-r--r-- | src/soc/intel/pantherlake/pcie_rp.c | 1 | ||||
-rw-r--r-- | src/soc/intel/pantherlake/romstage/fsp_params.c | 7 | ||||
-rw-r--r-- | src/soc/intel/pantherlake/soc_info.c | 52 |
7 files changed, 3 insertions, 84 deletions
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk index 10ef8e949f..f3403b5143 100644 --- a/src/soc/intel/pantherlake/Makefile.mk +++ b/src/soc/intel/pantherlake/Makefile.mk @@ -18,14 +18,12 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/pcd.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c -bootblock-y += soc_info.c romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c romstage-y += espi.c romstage-y += meminit.c romstage-y += pcie_rp.c romstage-y += reset.c -romstage-y += soc_info.c ramstage-y += acpi.c ramstage-y += chip.c @@ -41,7 +39,6 @@ ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += retimer.c -ramstage-y += soc_info.c ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += tcss.c @@ -52,7 +49,6 @@ smm-y += gpio.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += soc_info.c smm-y += uart.c smm-y += xhci.c CPPFLAGS_common += -I$(src)/soc/intel/pantherlake diff --git a/src/soc/intel/pantherlake/cpu.c b/src/soc/intel/pantherlake/cpu.c index 7856383339..1b81856afc 100644 --- a/src/soc/intel/pantherlake/cpu.c +++ b/src/soc/intel/pantherlake/cpu.c @@ -20,7 +20,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -#include <soc/soc_info.h> bool cpu_soc_is_in_untrusted_mode(void) { diff --git a/src/soc/intel/pantherlake/elog.c b/src/soc/intel/pantherlake/elog.c index fce408f222..7750058be4 100644 --- a/src/soc/intel/pantherlake/elog.c +++ b/src/soc/intel/pantherlake/elog.c @@ -8,7 +8,6 @@ #include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/soc_info.h> #include <types.h> struct pme_map { @@ -30,9 +29,6 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) static void pch_log_rp_wake_source(void) { - size_t i; - uint8_t max_port = get_max_pcie_port(); - const struct pme_map pme_map[] = { { PCI_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, { PCI_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, @@ -50,7 +46,7 @@ static void pch_log_rp_wake_source(void) #endif }; - for (i = 0; i < MIN(max_port, ARRAY_SIZE(pme_map)); ++i) { + for (size_t i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); i++) { if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(pme_map[i].devfn), PCI_FUNC(pme_map[i].devfn)))) elog_add_event_wake(pme_map[i].wake_source, 0); diff --git a/src/soc/intel/pantherlake/include/soc/soc_info.h b/src/soc/intel/pantherlake/include/soc/soc_info.h deleted file mode 100644 index c90eb44fc4..0000000000 --- a/src/soc/intel/pantherlake/include/soc/soc_info.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_PANTHERLAKE_SOC_INFO_H_ -#define _SOC_PANTHERLAKE_SOC_INFO_H_ - -uint8_t get_max_usb20_port(void); -uint8_t get_max_usb30_port(void); -uint8_t get_max_tcss_port(void); -uint8_t get_max_tbt_pcie_port(void); -uint8_t get_max_pcie_port(void); -uint8_t get_max_pcie_clock(void); -uint8_t get_max_uart_port(void); -uint8_t get_max_i2c_port(void); -uint8_t get_max_gspi_port(void); - -#endif /* _SOC_PANTHERLAKE_SOC_INFO_H_ */ diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c index 374c3aa1e1..1b302fda0e 100644 --- a/src/soc/intel/pantherlake/pcie_rp.c +++ b/src/soc/intel/pantherlake/pcie_rp.c @@ -3,7 +3,6 @@ #include <intelblocks/pcie_rp.h> #include <soc/pci_devs.h> #include <soc/pcie.h> -#include <soc/soc_info.h> /* * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 2a7891b7d0..f6ba498191 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -9,7 +9,6 @@ #include <soc/msr.h> #include <soc/pcie.h> #include <soc/romstage.h> -#include <soc/soc_info.h> #define FSP_CLK_NOTUSED 0xff #define FSP_CLK_LAN 0x70 @@ -197,9 +196,7 @@ static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_pantherlake_config *config) { /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ - uint8_t max_clock = get_max_pcie_clock(); - - for (size_t i = 0; i < max_clock; i++) { + for (size_t i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) @@ -212,7 +209,7 @@ static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, /* PCIE ports */ m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table()); pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp, - get_max_pcie_port()); + CONFIG_MAX_ROOT_PORTS); } static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, diff --git a/src/soc/intel/pantherlake/soc_info.c b/src/soc/intel/pantherlake/soc_info.c deleted file mode 100644 index 275d56876c..0000000000 --- a/src/soc/intel/pantherlake/soc_info.c +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/pci_devs.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <soc/soc_info.h> -#include <intelblocks/tcss.h> - -uint8_t get_max_usb20_port(void) -{ - return CONFIG_SOC_INTEL_USB2_DEV_MAX; -} - -uint8_t get_max_usb30_port(void) -{ - return CONFIG_SOC_INTEL_USB3_DEV_MAX; -} - -uint8_t get_max_tcss_port(void) -{ - return MAX_TYPE_C_PORTS; -} - -uint8_t get_max_tbt_pcie_port(void) -{ - return CONFIG_MAX_TBT_ROOT_PORTS; -} - -uint8_t get_max_pcie_port(void) -{ - return CONFIG_MAX_ROOT_PORTS; -} - -uint8_t get_max_pcie_clock(void) -{ - return CONFIG_MAX_PCIE_CLOCK_SRC; -} - -uint8_t get_max_uart_port(void) -{ - return CONFIG_SOC_INTEL_UART_DEV_MAX; -} - -uint8_t get_max_i2c_port(void) -{ - return CONFIG_SOC_INTEL_I2C_DEV_MAX; -} - -uint8_t get_max_gspi_port(void) -{ - return CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; -} |