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-rw-r--r--src/soc/intel/xeon_sp/bootblock.c6
-rw-r--r--src/soc/intel/xeon_sp/nb_acpi.c2
-rw-r--r--src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h4
-rw-r--r--src/soc/intel/xeon_sp/skx/soc_util.c20
4 files changed, 16 insertions, 16 deletions
diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
index 1d706fe9c9..5ea09ac3a7 100644
--- a/src/soc/intel/xeon_sp/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -56,9 +56,9 @@ void bootblock_soc_early_init(void)
pch_enable_lpc();
/* Set up P2SB BAR. This is needed for PCR to work */
- uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND);
- pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY);
- pci_mmio_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
+ uint8_t p2sb_cmd = pci_s_read_config8(PCH_DEV_P2SB, PCI_COMMAND);
+ pci_s_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY);
+ pci_s_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
}
void bootblock_soc_init(void)
diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c
index 0c1c5ab30d..9443966237 100644
--- a/src/soc/intel/xeon_sp/nb_acpi.c
+++ b/src/soc/intel/xeon_sp/nb_acpi.c
@@ -160,7 +160,7 @@ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current,
const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device;
const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function;
- const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func),
+ const uint32_t id = pci_s_read_config32(PCI_DEV(bus, dev, func),
PCI_VENDOR_ID);
if (id == 0xffffffff)
return 0;
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 01e86e199f..4b46ec890b 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -13,13 +13,13 @@
printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \
fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \
((uint32_t)dev >> 12) & 0x07, \
- #reg, reg, pci_mmio_read_config32(dev, reg))
+ #reg, reg, pci_s_read_config32(dev, reg))
#define dump_csr64(fmt, dev, reg) \
printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x%x\n", \
fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \
((uint32_t)dev >> 12) & 0x07, #reg, reg, \
- pci_mmio_read_config32(dev, reg+4), pci_mmio_read_config32(dev, reg))
+ pci_s_read_config32(dev, reg+4), pci_s_read_config32(dev, reg))
#define SAD_ALL_DEV 29
#define SAD_ALL_FUNC 0
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index b903249e1d..cc8db642b8 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -79,11 +79,11 @@ void config_reset_cpl3_csrs(void)
/* configure PCU_CR0_FUN csrs */
pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN);
- data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS);
+ data = pci_s_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS);
data |= P_STATE_LIMITS_LOCK;
- pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data);
+ pci_s_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data);
- plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO);
+ plat_info = pci_s_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO);
dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO);
max_min_turbo_limit_ratio =
(plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
@@ -94,29 +94,29 @@ void config_reset_cpl3_csrs(void)
/* configure PCU_CR1_FUN csrs */
pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
- data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL);
+ data = pci_s_read_config32(cr1_dev, PCU_CR1_SAPMCTL);
/* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
data &= 0x0fffffff;
data |= SAPMCTL_LOCK_MASK;
- pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data);
+ pci_s_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data);
/* configure PCU_CR1_FUN csrs */
pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN);
data = PCIE_IN_PKGCSTATE_L1_MASK;
- pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
+ pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
data = KTI_IN_PKGCSTATE_L1_MASK;
- pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
+ pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
data = PROCHOT_RATIO;
printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
- pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
+ pci_s_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
- data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
+ data = pci_s_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
- pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
+ pci_s_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
}
}