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-rw-r--r--src/soc/amd/cezanne/romstage.c3
-rw-r--r--src/soc/amd/picasso/romstage.c2
2 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 773c6a97d5..2740d8c74c 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -29,9 +29,6 @@ asmlinkage void car_stage_entry(void)
post_code(0x41);
- u32 val = cpuid_eax(1);
- printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
-
fsp_memory_init(acpi_is_wakeup_s3());
memmap_stash_early_dram_usage();
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index aa8da1ea69..c085a5355f 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -147,8 +147,6 @@ asmlinkage void car_stage_entry(void)
console_init();
post_code(0x42);
- u32 val = cpuid_eax(1);
- printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
/* Snapshot chipset state prior to any FSP call. */
fill_chipset_state();