diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 13 |
2 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 813974909a..00088b9aad 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -200,6 +200,11 @@ struct soc_intel_skylake_config { u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS]; /* + * Clk source number for Root Port + */ + u8 PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS]; + + /* * Enable/Disable AER (Advanced Error Reporting) for Root Port * 0: Disable AER * 1: Enable AER diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 96c3b608af..24a239e3b5 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -166,6 +166,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); + /* + * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for + * all the enabled PCIe root ports, invalid(0x1F) is set for + * disabled PCIe root ports. + */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + if (config->PcieRpClkReqSupport[i]) + params->PcieRpClkSrcNumber[i] = + config->PcieRpClkSrcNumber[i]; + else + params->PcieRpClkSrcNumber[i] = 0x1F; + } + /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); |