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-rw-r--r--src/soc/intel/fsp_baytrail/Kconfig8
-rw-r--r--src/soc/intel/fsp_baytrail/Makefile.inc2
2 files changed, 1 insertions, 9 deletions
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 689e625535..549ea55d19 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -95,14 +95,6 @@ config VGA_BIOS_FILE
string
default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS
-config FSP_BAYTRAIL_GFX_INIT
- default n
- bool
- help
- Enabling this option will activate graphics init code. With this init,
- the graphic power gate registers will be initialized before
- VBIOS is executed.
-
config CPU_MICROCODE_HEADER_FILES
string
default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h"
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 6e16b426a0..f0866652c4 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -57,7 +57,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
ramstage-y += placeholders.c
ramstage-y += i2c.c
-ramstage-$(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c
+ramstage-y += gfx.c
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp