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-rw-r--r--src/soc/intel/cannonlake/acpi.c82
-rw-r--r--src/soc/intel/cannonlake/include/soc/iomap.h9
-rw-r--r--src/soc/intel/cannonlake/include/soc/systemagent.h27
-rw-r--r--src/soc/intel/cannonlake/systemagent.c13
4 files changed, 130 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 639f6c6f90..43d91d3f83 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -17,19 +17,22 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
-#include <device/mmio.h>
#include <arch/smp/mpspec.h>
#include <cbmem.h>
#include <chip.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
+#include <intelblocks/p2sb.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
+#include <soc/systemagent.h>
#include <string.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <wrdd.h>
@@ -285,3 +288,80 @@ int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
}
+
+static unsigned long soc_fill_dmar(unsigned long current)
+{
+ struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+ uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
+ bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
+
+ if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) {
+ unsigned long tmp = current;
+
+ current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+
+ acpi_dmar_drhd_fixup(tmp, current);
+
+ /* Add RMRR entry */
+ tmp = current;
+ current += acpi_create_dmar_rmrr(current, 0,
+ sa_get_gsm_base(), sa_get_tolud_base() - 1);
+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+ acpi_dmar_rmrr_fixup(tmp, current);
+ }
+
+ struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU);
+ uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
+ bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
+
+ if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) {
+ unsigned long tmp = current;
+
+ current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
+ current += acpi_create_dmar_ds_pci(current, 0, 5, 0);
+
+ acpi_dmar_drhd_fixup(tmp, current);
+ }
+
+ uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
+ bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
+
+ if (vtvc0bar && vtvc0en) {
+ const unsigned long tmp = current;
+
+ current += acpi_create_dmar_drhd(current,
+ DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
+ current += acpi_create_dmar_ds_ioapic(current,
+ 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
+ V_P2SB_CFG_IBDF_FUNC);
+ current += acpi_create_dmar_ds_msi_hpet(current,
+ 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
+ V_P2SB_CFG_HBDF_FUNC);
+
+ acpi_dmar_drhd_fixup(tmp, current);
+ }
+
+ return current;
+}
+
+unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current,
+ struct acpi_rsdp *rsdp)
+{
+ acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
+
+ /* Create DMAR table only if we have VT-d capability
+ * and FSP does not override its feature.
+ */
+ if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
+ !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
+ return current;
+
+ printk(BIOS_DEBUG, "ACPI: * DMAR\n");
+ acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar);
+ current += dmar->header.length;
+ current = acpi_align_current(current);
+ acpi_add_table(rsdp, dmar);
+
+ return current;
+}
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index ed9b29ffee..100bd11356 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -52,6 +52,15 @@
#define EDRAM_BASE_ADDRESS 0xfed80000
#define EDRAM_BASE_SIZE 0x4000
+#define GFXVT_BASE_ADDRESS 0xfed90000
+#define GFXVT_BASE_SIZE 0x1000
+
+#define IPUVT_BASE_ADDRESS 0xfed92000
+#define IPUVT_BASE_SIZE 0x1000
+
+#define VTVC0_BASE_ADDRESS 0xfed91000
+#define VTVC0_BASE_SIZE 0x1000
+
#define REG_BASE_ADDRESS 0xfc000000
#define REG_BASE_SIZE 0x1000
diff --git a/src/soc/intel/cannonlake/include/soc/systemagent.h b/src/soc/intel/cannonlake/include/soc/systemagent.h
index da83c381a0..3bda9e8d59 100644
--- a/src/soc/intel/cannonlake/include/soc/systemagent.h
+++ b/src/soc/intel/cannonlake/include/soc/systemagent.h
@@ -30,10 +30,17 @@
#define D_LCK (1 << 4)
#define G_SMRAME (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+#define CAPID0_A 0xe4
+#define VTD_DISABLE (1 << 23)
#define BIOS_RESET_CPL 0x5da8
+#define GFXVTBAR 0x5400
#define EDRAMBAR 0x5408
+#define IPUVTBAR 0x7880
+#define VTVC0BAR 0x5410
#define REGBAR 0x5420
+#define VTBAR_ENABLED 0x01
+#define VTBAR_MASK 0x7ffffff000ull
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
#define MCH_PKG_POWER_LIMIT_HI 0x59a4
@@ -43,4 +50,24 @@
#define IMRBASE 0x6A40
#define IMRLIMIT 0x6A48
+#if CONFIG(SOC_INTEL_COFFEELAKE) || CONFIG(SOC_INTEL_WHISKEYLAKE) \
+ || CONFIG(SOC_INTEL_COMETLAKE)
+static const struct sa_mmio_descriptor soc_vtd_resources[] = {
+ { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
+ { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
+};
+#else
+static const struct sa_mmio_descriptor soc_vtd_resources[] = {
+ { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
+ { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" },
+ { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
+};
+#endif
+
+#define V_P2SB_CFG_IBDF_BUS 0
+#define V_P2SB_CFG_IBDF_DEV 30
+#define V_P2SB_CFG_IBDF_FUNC 7
+#define V_P2SB_CFG_HBDF_BUS 0
+#define V_P2SB_CFG_HBDF_DEV 30
+#define V_P2SB_CFG_HBDF_FUNC 6
#endif
diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c
index 9c8d761648..d850b15b34 100644
--- a/src/soc/intel/cannonlake/systemagent.c
+++ b/src/soc/intel/cannonlake/systemagent.c
@@ -18,10 +18,12 @@
#include <device/device.h>
#include <delay.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <intelblocks/systemagent.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/systemagent.h>
+#include "chip.h"
/*
* SoC implementation
@@ -31,6 +33,8 @@
*/
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
+ const struct soc_intel_cannonlake_config *const config = dev->chip_info;
+
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
"PCIEXBAR" },
@@ -54,6 +58,15 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
ARRAY_SIZE(soc_fixed_resources));
+
+ /* Add Vt-d resources if VT-d is enabled. */
+ if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
+ return;
+
+ if (!(config && config->VtdDisable)) {
+ sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
+ ARRAY_SIZE(soc_vtd_resources));
+ }
}
/*
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 04:20:51 +0000