diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 2 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/spi_bitbang.c | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index bccd455a2a..d3a28413a8 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -434,7 +434,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK select ARCH_VERSTAGE_ARMV7 help Runs verstage on the PSP. Only available on - certain Chrome OS branded parts from AMD. + certain ChromeOS branded parts from AMD. config VBOOT_HASH_BLOCK_SIZE hex diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 88ae228fb5..2a056a2452 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -466,7 +466,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK select ARCH_VERSTAGE_ARMV7 help Runs verstage on the PSP. Only available on - certain Chrome OS branded parts from AMD. + certain ChromeOS branded parts from AMD. config VBOOT_HASH_BLOCK_SIZE hex diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 2e9022f24c..654c6e3935 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -454,7 +454,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK select ARCH_VERSTAGE_ARMV7 help Runs verstage on the PSP. Only available on - certain Chrome OS branded parts from AMD. + certain ChromeOS branded parts from AMD. config VBOOT_HASH_BLOCK_SIZE hex diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 322e9f3d02..f7aae1c0cd 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -490,7 +490,7 @@ uint8_t cse_wait_com_soft_temp_disable(void); /* * The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set - * CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to + * CSE's boot partition as per ChromeOS boot modes. In normal mode, the function allows CSE to * boot from RW and triggers recovery mode if CSE fails to jump to RW. * In software triggered recovery mode, the function allows CSE to boot from whatever is * currently selected partition. diff --git a/src/soc/rockchip/rk3399/spi_bitbang.c b/src/soc/rockchip/rk3399/spi_bitbang.c index 27b23f1ea3..8bc45e50be 100644 --- a/src/soc/rockchip/rk3399/spi_bitbang.c +++ b/src/soc/rockchip/rk3399/spi_bitbang.c @@ -46,7 +46,7 @@ static void set_cs(const struct spi_bitbang_ops *ops, int value) gpio_set(slave->cs, value); } -/* Can't use GPIO() here because of bug in GCC version used by Chromium OS. */ +/* Can't use GPIO() here because of bug in GCC version used by ChromiumOS. */ static const struct rockchip_bitbang_slave slaves[] = { [0] = { .ops = { get_miso, set_mosi, set_clk, set_cs }, |