diff options
Diffstat (limited to 'src/soc')
24 files changed, 243 insertions, 137 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 371d0c4cb6..42ff3bdf39 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -70,6 +70,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_DSP select SOC_INTEL_COMMON_BLOCK_FAST_SPI @@ -392,6 +393,10 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 3 +config SOC_INTEL_I2C_DEV_MAX + int + default 8 + # Don't include the early page tables in RW_A or RW_B cbfs regions config RO_REGION_ONLY string diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index af465df111..4f586acfd1 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -20,6 +20,7 @@ #define _SOC_APOLLOLAKE_CHIP_H_ #include <commonlib/helpers.h> +#include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -31,7 +32,6 @@ #define MAX_PCIE_PORTS 6 #define CLKREQ_DISABLED 0xf -#define APOLLOLAKE_I2C_DEV_MAX 8 enum pnp_settings { PNP_PERF, @@ -40,8 +40,9 @@ enum pnp_settings { }; struct soc_intel_apollolake_config { - /* GSPI */ - struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* Common structure containing soc config data required by common code*/ + struct soc_intel_common_config common_soc_config; /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has @@ -98,9 +99,6 @@ struct soc_intel_apollolake_config { /* Configure serial IRQ (SERIRQ) line. */ enum serirq_mode serirq_mode; - /* I2C bus configuration */ - struct dw_i2c_bus_config i2c[APOLLOLAKE_I2C_DEV_MAX]; - uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ diff --git a/src/soc/intel/apollolake/gspi.c b/src/soc/intel/apollolake/gspi.c index 6d5f8e59dc..af32ebd5a0 100644 --- a/src/soc/intel/apollolake/gspi.c +++ b/src/soc/intel/apollolake/gspi.c @@ -24,19 +24,10 @@ const struct gspi_cfg *gspi_get_soc_cfg(void) { - DEVTREE_CONST struct soc_intel_apollolake_config *config; - int devfn = SA_DEVFN_ROOT; - DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn); + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - config = dev->chip_info; - - return &config->gspi[0]; + return &common_config->gspi[0]; } uintptr_t gspi_get_soc_early_base(void) diff --git a/src/soc/intel/apollolake/i2c.c b/src/soc/intel/apollolake/i2c.c index 3df333c869..bb14df2a0e 100644 --- a/src/soc/intel/apollolake/i2c.c +++ b/src/soc/intel/apollolake/i2c.c @@ -17,24 +17,17 @@ #include <device/device.h> #include <device/pci_def.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <intelblocks/chip.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include "chip.h" const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { - const struct soc_intel_apollolake_config *config; - const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - config = dev->chip_info; - - return &config->i2c[bus]; + return &common_config->i2c[bus]; } uintptr_t dw_i2c_get_soc_early_base(unsigned int bus) diff --git a/src/soc/intel/apollolake/include/soc/soc_chip.h b/src/soc/intel/apollolake/include/soc/soc_chip.h new file mode 100644 index 0000000000..fa53a15906 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/soc_chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_SOC_CHIP_H_ +#define _SOC_APOLLOLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_APOLLOLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f50d9f2bd6..5d8883bc9c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 @@ -188,6 +189,10 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 3 +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 47f06aa47d..86f147d0c3 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += gpio.c ramstage-y += i2c.c +ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += nhlt.c diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index d943f9c781..a269659f12 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -18,6 +18,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ +#include <intelblocks/chip.h> #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/gspi.h> #include <stdint.h> @@ -30,11 +31,10 @@ #include <soc/usb.h> #include <soc/vr_config.h> -#define CANNONLAKE_I2C_DEV_MAX 6 - struct soc_intel_cannonlake_config { - /* GSPI */ - struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; /* Interrupt Routing configuration. * If bit7 is 1, the interrupt is disabled. */ @@ -201,11 +201,6 @@ struct soc_intel_cannonlake_config { uint8_t TcoIrqSelect; uint8_t TcoIrqEnable; - enum { - CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ - CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ - } chipset_lockdown; - /* * Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init @@ -281,9 +276,6 @@ struct soc_intel_cannonlake_config { /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; - /* I2C bus configuration */ - struct dw_i2c_bus_config i2c[CANNONLAKE_I2C_DEV_MAX]; - /* Enable Pch iSCLK */ uint8_t pch_isclk; diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c index e4f682db42..4b00f3a0f8 100644 --- a/src/soc/intel/cannonlake/gspi.c +++ b/src/soc/intel/cannonlake/gspi.c @@ -16,6 +16,7 @@ #include <assert.h> #include <device/device.h> +#include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <intelblocks/spi.h> #include <soc/iomap.h> @@ -24,19 +25,10 @@ const struct gspi_cfg *gspi_get_soc_cfg(void) { - DEVTREE_CONST struct soc_intel_cannonlake_config *config; - int devfn = SA_DEVFN_ROOT; - DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn); + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - config = dev->chip_info; - - return &config->gspi[0]; + return &common_config->gspi[0]; } uintptr_t gspi_get_soc_early_base(void) diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c index ef3034537f..b53d5a0c1c 100644 --- a/src/soc/intel/cannonlake/i2c.c +++ b/src/soc/intel/cannonlake/i2c.c @@ -18,24 +18,17 @@ #include <device/device.h> #include <device/pci_def.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <intelblocks/chip.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include "chip.h" const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { - const struct soc_intel_cannonlake_config *config; - const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - config = dev->chip_info; - - return &config->i2c[bus]; + return &common_config->i2c[bus]; } uintptr_t dw_i2c_get_soc_early_base(unsigned int bus) diff --git a/src/soc/intel/cannonlake/include/soc/soc_chip.h b/src/soc/intel/cannonlake/include/soc/soc_chip.h new file mode 100644 index 0000000000..3d6f232530 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/soc_chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CANNONLAKE_SOC_CHIP_H_ +#define _SOC_CANNONLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_CANNONLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index 7a3b0c0130..1f1e654636 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <bootstate.h> #include <chip.h> +#include <intelblocks/chip.h> #include <intelblocks/fast_spi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> @@ -27,15 +28,15 @@ #define PCR_DMI_GCS 0x274C #define PCR_DMI_GCS_BILD (1 << 0) -static void pmc_lockdown_cfg(const struct soc_intel_cannonlake_config *config) +static void pmc_lockdown_cfg(const struct soc_intel_common_config *config) { - uint8_t *pmcbase; + uint8_t *pmcbase, reg8; uint32_t reg32, pmsyncreg; /* PMSYNC */ pmcbase = pmc_mmio_regs(); pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); - pmsyncreg |= PMSYNC_LOCK; + pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); /* Lock down ABASE and sleep stretching policy */ @@ -66,7 +67,7 @@ static void dmi_lockdown_cfg(void) pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); } -static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config) +static void fast_spi_lockdown_cfg(const struct soc_intel_common_config *config) { /* Set FAST_SPI opcode menu */ fast_spi_set_opcode_menu(); @@ -89,24 +90,17 @@ static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config) static void platform_lockdown_config(void *unused) { - struct soc_intel_cannonlake_config *config; - struct device *dev; - - dev = PCH_DEV_SPI; - /* Check if device is valid, else return */ - if (dev == NULL || dev->chip_info == NULL) - return; - - config = dev->chip_info; + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); /* SPI lock down configuration */ - spi_lockdown_cfg(config); + fast_spi_lockdown_cfg(common_config); /* DMI lock down configuration */ dmi_lockdown_cfg(); /* PMC lock down configuration */ - pmc_lockdown_cfg(config); + pmc_lockdown_cfg(common_config); } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, diff --git a/src/soc/intel/common/block/chip/Kconfig b/src/soc/intel/common/block/chip/Kconfig new file mode 100644 index 0000000000..273d0885e8 --- /dev/null +++ b/src/soc/intel/common/block/chip/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + bool + help + Intel Processor common soc/ chip configuration support diff --git a/src/soc/intel/common/block/chip/Makefile.inc b/src/soc/intel/common/block/chip/Makefile.inc new file mode 100644 index 0000000000..425d5a24c8 --- /dev/null +++ b/src/soc/intel/common/block/chip/Makefile.inc @@ -0,0 +1,10 @@ +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG),y) + +bootblock-y += chip.c +romstage-y += chip.c +verstage-y += chip.c +ramstage-y += chip.c +smm-y += chip.c +postcar-y += chip.c + +endif diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c new file mode 100644 index 0000000000..cfec4eca39 --- /dev/null +++ b/src/soc/intel/common/block/chip/chip.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <soc/pci_devs.h> +#include <soc/soc_chip.h> + +const struct soc_intel_common_config *chip_get_common_soc_structure(void) +{ + const struct soc_intel_common_config *soc_config; + const config_t *config; + int devfn = SA_DEVFN_ROOT; + const struct device *dev = dev_find_slot(0, devfn); + + if (!dev || !dev->chip_info) + die("Could not find SA_DEV_ROOT devicetree config!\n"); + + config = dev->chip_info; + soc_config = &config->common_soc_config; + + return soc_config; +} diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h new file mode 100644 index 0000000000..555bdaa893 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/chip.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_CHIP_H +#define SOC_INTEL_COMMON_BLOCK_CHIP_H + +#include <intelblocks/gspi.h> +#include <drivers/i2c/designware/dw_i2c.h> + +enum { + CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ + CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ +}; + +/* + * This structure will hold data required by common blocks. + * These are soc specific configurations which will be filled by soc. + * We'll fill this structure once during init and use the data in common block. + */ +struct soc_intel_common_config { + int chipset_lockdown; + struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; +}; + +/* This function to retrieve soc config structure required by common code */ +const struct soc_intel_common_config *chip_get_common_soc_structure(void); + +#endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */ diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index bfaa19f5d6..13b18dc151 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS @@ -329,6 +330,10 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 2 +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + config CPU_BCLK_MHZ int default 100 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 9fe19d8f9b..466db0950e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -69,6 +69,14 @@ static void soc_enable(struct device *dev) dev->ops = &cpu_bus_ops; } +static int get_lockdown_config(void) +{ + const struct soc_intel_common_config *soc_config; + soc_config = chip_get_common_soc_structure(); + + return soc_config->chipset_lockdown; +} + struct chip_operations soc_intel_skylake_ops = { CHIP_NAME("Intel Skylake") .enable_dev = &soc_enable, @@ -145,7 +153,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SataMode = config->SataMode; params->LockDownConfigGlobalSmi = config->LockDownConfigGlobalSmi; params->LockDownConfigRtcLock = config->LockDownConfigRtcLock; - if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { params->LockDownConfigBiosInterface = 0; params->LockDownConfigBiosLock = 0; params->LockDownConfigSpiEiss = 0; @@ -173,7 +181,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SkipMpInit = !config->use_fsp_mp_init; - for (i = 0; i < ARRAY_SIZE(config->i2c); i++) + for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; /* diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 8b98662b1e..3c85ad5a3d 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +22,7 @@ #include <arch/acpi_device.h> #include <device/i2c_simple.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <stdint.h> #include <soc/gpe.h> @@ -33,14 +34,16 @@ #include <soc/usb.h> #include <soc/vr_config.h> -#define SKYLAKE_I2C_DEV_MAX 6 - enum skylake_i2c_voltage { I2C_VOLTAGE_3V3, I2C_VOLTAGE_1V8 }; struct soc_intel_skylake_config { + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + /* * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. @@ -273,11 +276,7 @@ struct soc_intel_skylake_config { /* I2C */ /* Bus voltage level, default is 3.3V */ - enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX]; - struct dw_i2c_bus_config i2c[SKYLAKE_I2C_DEV_MAX]; - - /* GSPI */ - struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX]; /* Camera */ u8 Cio2Enable; @@ -544,16 +543,6 @@ struct soc_intel_skylake_config { * 0b - Disabled */ u8 eist_enable; - /* Chipset (LPC and SPI) Lock Down - * 1b - coreboot to handle lockdown - * 0b - FSP to handle lockdown - */ - enum { - /* lock according to binary UPD settings */ - CHIPSET_LOCKDOWN_FSP, - /* coreboot handles locking */ - CHIPSET_LOCKDOWN_COREBOOT, - } chipset_lockdown; /* * Activates VR mailbox command for Intersil VR C-state issues. diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 227e244224..ebfad667bb 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -211,6 +211,14 @@ static void soc_enable(struct device *dev) dev->ops = &cpu_bus_ops; } +static int get_lockdown_config(void) +{ + const struct soc_intel_common_config *soc_config; + soc_config = chip_get_common_soc_structure(); + + return soc_config->chipset_lockdown; +} + struct chip_operations soc_intel_skylake_ops = { CHIP_NAME("Intel 6th Gen") .enable_dev = &soc_enable, @@ -352,7 +360,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * do the changes and then lock it back in coreboot during finalize. */ tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; - if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { tconfig->PchLockDownBiosInterface = 0; params->PchLockDownBiosLock = 0; params->PchLockDownSpiEiss = 0; @@ -389,7 +397,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init; - for (i = 0; i < ARRAY_SIZE(config->i2c); i++) + for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c index 252be7771c..ed36c7a15a 100644 --- a/src/soc/intel/skylake/gspi.c +++ b/src/soc/intel/skylake/gspi.c @@ -16,6 +16,7 @@ #include <assert.h> #include <device/device.h> +#include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <intelblocks/spi.h> #include <soc/iomap.h> @@ -23,19 +24,10 @@ const struct gspi_cfg *gspi_get_soc_cfg(void) { - DEVTREE_CONST struct soc_intel_skylake_config *config; - int devfn = SA_DEVFN_ROOT; - DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn); + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - config = dev->chip_info; - - return &config->gspi[0]; + return &common_config->gspi[0]; } uintptr_t gspi_get_soc_early_base(void) diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index baf6335ced..c9070fe5a0 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <device/device.h> +#include <intelblocks/chip.h> #include <drivers/i2c/designware/dw_i2c.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -22,18 +23,10 @@ const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { - const struct soc_intel_skylake_config *config; - const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - config = dev->chip_info; - - return &config->i2c[bus]; + return &common_config->i2c[bus]; } uintptr_t dw_i2c_get_soc_early_base(unsigned int bus) diff --git a/src/soc/intel/skylake/include/soc/soc_chip.h b/src/soc/intel/skylake/include/soc/soc_chip.h new file mode 100644 index 0000000000..f9e7e4fc64 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/soc_chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_SKYLAKE_SOC_CHIP_H_ +#define _SOC_SKYLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_SKYLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 600be27957..fd1f5b2206 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <bootstate.h> #include <chip.h> +#include <intelblocks/chip.h> #include <intelblocks/fast_spi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> @@ -27,7 +28,7 @@ #define PCR_DMI_GCS 0x274C #define PCR_DMI_GCS_BILD (1 << 0) -static void lpc_lockdown_config(const struct soc_intel_skylake_config *config) +static void lpc_lockdown_config(const struct soc_intel_common_config *config) { /* Set Bios Interface Lock, Bios Lock */ if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { @@ -63,7 +64,8 @@ static void dmi_lockdown_config(void) pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); } -static void spi_lockdown_config(const struct soc_intel_skylake_config *config) +static void fast_spi_lockdown_config(const + struct soc_intel_common_config *config) { /* Set FAST_SPI opcode menu */ fast_spi_set_opcode_menu(); @@ -86,21 +88,14 @@ static void spi_lockdown_config(const struct soc_intel_skylake_config *config) static void platform_lockdown_config(void *unused) { - struct soc_intel_skylake_config *config; - struct device *dev; - - dev = PCH_DEV_SPI; - /* Check if device is valid, else return */ - if (dev == NULL || dev->chip_info == NULL) - return; - - config = dev->chip_info; + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); /* LPC lock down configuration */ - lpc_lockdown_config(config); + lpc_lockdown_config(common_config); /* SPI lock down configuration */ - spi_lockdown_config(config); + fast_spi_lockdown_config(common_config); /* DMI lock down configuration */ dmi_lockdown_config(); |