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-rw-r--r--src/soc/intel/apollolake/chip.c8
-rw-r--r--src/soc/intel/apollolake/include/FspUpd.h48
-rw-r--r--src/soc/intel/apollolake/include/soc/fsp/FspUpd.h6
-rw-r--r--src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h282
-rw-r--r--src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h552
-rw-r--r--src/soc/intel/apollolake/include/soc/meminit.h9
-rw-r--r--src/soc/intel/apollolake/include/soc/romstage.h2
-rw-r--r--src/soc/intel/apollolake/meminit.c20
-rw-r--r--src/soc/intel/apollolake/reset.c2
-rw-r--r--src/soc/intel/apollolake/romstage.c6
10 files changed, 498 insertions, 437 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1b109d0c93..9cec08dcec 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -231,7 +231,7 @@ static void soc_final(void *data)
global_reset_lock();
}
-static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
+static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) {
switch (dev->path.pci.devfn) {
case ISH_DEVFN:
@@ -335,7 +335,7 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
}
}
-static void parse_devicetree(struct FSP_S_CONFIG *silconfig)
+static void parse_devicetree(FSP_S_CONFIG *silconfig)
{
struct device *dev = NB_DEV_ROOT;
@@ -350,9 +350,9 @@ static void parse_devicetree(struct FSP_S_CONFIG *silconfig)
}
}
-void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
{
- struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
+ FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
static struct soc_intel_apollolake_config *cfg;
/* Load VBT before devicetree-specific config. */
diff --git a/src/soc/intel/apollolake/include/FspUpd.h b/src/soc/intel/apollolake/include/FspUpd.h
new file mode 100644
index 0000000000..a7114ce39e
--- /dev/null
+++ b/src/soc/intel/apollolake/include/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(push, 1)
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
+
+#pragma pack(pop)
+
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h
index 4d865f5e8d..a7114ce39e 100644
--- a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h
+++ b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h
@@ -33,10 +33,16 @@ are permitted provided that the following conditions are met:
#ifndef __FSPUPD_H__
#define __FSPUPD_H__
+#include <FspEas.h>
+
+#pragma pack(push, 1)
+
#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
+#pragma pack(pop)
+
#endif
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
index 88d4c42017..48225e0779 100644
--- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
+++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
@@ -33,87 +33,89 @@ are permitted provided that the following conditions are met:
#ifndef __FSPMUPD_H__
#define __FSPMUPD_H__
-#include "FspUpd.h"
-#include <fsp/upd.h>
+#include <FspUpd.h>
+
+#pragma pack(push, 1)
+
#define MAX_CHANNELS_NUM 4
#define MAX_DIMMS_NUM 1
-struct DIMM_INFO {
- uint8_t DimmId;
- uint32_t SizeInMb;
- uint16_t MfgId;
+typedef struct {
+ UINT8 DimmId;
+ UINT32 SizeInMb;
+ UINT16 MfgId;
/** Module part number for DRR3 is 18 bytes
but DRR4 is 20 bytes as per JEDEC Spec, so
reserving 20 bytes **/
- uint8_t ModulePartNum[20];
-} __attribute__((packed));
-
-struct CHANNEL_INFO {
- uint8_t ChannelId;
- uint8_t DimmCount;
- struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
-} __attribute__((packed));
-
-struct FSP_SMBIOS_MEMORY_INFO {
- uint8_t Revision;
- uint8_t DataWidth;
+ UINT8 ModulePartNum[20];
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 ChannelId;
+ UINT8 DimmCount;
+ DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT8 DataWidth;
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
- uint16_t MemoryType;
- uint16_t MemoryFrequencyInMHz;
+ UINT16 MemoryType;
+ UINT16 MemoryFrequencyInMHz;
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
- uint8_t ErrorCorrectionType;
- uint8_t ChannelCount;
- struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
-} __attribute__((packed));
+ UINT8 ErrorCorrectionType;
+ UINT8 ChannelCount;
+ CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
+} FSP_SMBIOS_MEMORY_INFO;
/** Fsp M Configuration
**/
-struct FSP_M_CONFIG {
+typedef struct {
/** Offset 0x0040 - Debug Serial Port Base address
Debug serial port base address. This option will be used only when the 'Serial Port
Debug Device' option is set to 'External Device'. 0x00000000(Default).
**/
- uint32_t SerialDebugPortAddress;
+ UINT32 SerialDebugPortAddress;
/** Offset 0x0044 - Debug Serial Port Type
16550 compatible debug serial port resource type. NONE means no serial port support.
0x02:MMIO(Default).
0:NONE, 1:I/O, 2:MMIO
**/
- uint8_t SerialDebugPortType;
+ UINT8 SerialDebugPortType;
/** Offset 0x0045 - Serial Port Debug Device
Select active serial port device for debug. For SOC UART devices,'Debug Serial Port
Base' options will be ignored. 0x02:SOC UART2(Default).
0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device
**/
- uint8_t SerialDebugPortDevice;
+ UINT8 SerialDebugPortDevice;
/** Offset 0x0046 - Debug Serial Port Stride Size
Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).
0:1, 2:4
**/
- uint8_t SerialDebugPortStrideSize;
+ UINT8 SerialDebugPortStrideSize;
/** Offset 0x0047 - Memory Fast Boot
Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default).
$EN_DIS
**/
- uint8_t MrcFastBoot;
+ UINT8 MrcFastBoot;
/** Offset 0x0048 - Integrated Graphics Device
Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video
Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default).
$EN_DIS
**/
- uint8_t Igd;
+ UINT8 Igd;
/** Offset 0x0049 - DVMT Pre-Allocated
Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal
@@ -122,35 +124,35 @@ struct FSP_M_CONFIG {
MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB,
0x0F:480 MB, 0x10:512 MB
**/
- uint8_t IgdDvmt50PreAlloc;
+ UINT8 IgdDvmt50PreAlloc;
/** Offset 0x004A - Aperture Size
Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default),
0x2:256 MB, 0x3:512 MB.
0x1:128 MB, 0x2:256 MB, 0x3:512 MB
**/
- uint8_t IgdApertureSize;
+ UINT8 IgdApertureSize;
/** Offset 0x004B - GTT Size
Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8
MB(Default).
0x1:2 MB, 0x2:4 MB, 0x3:8 MB
**/
- uint8_t GttSize;
+ UINT8 GttSize;
/** Offset 0x004C - Primary Display
Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default),
0x2:IGD, 0x3:PCI
0x0:AUTO, 0x2:IGD, 0x3:PCI
**/
- uint8_t PrimaryVideoAdaptor;
+ UINT8 PrimaryVideoAdaptor;
/** Offset 0x004D - Package
NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L
is being used. 0x00(Default).
0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD
**/
- uint8_t Package;
+ UINT8 Package;
/** Offset 0x004E - Profile
Profile list. 0x19(Default).
@@ -167,127 +169,127 @@ struct FSP_M_CONFIG {
0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15,
0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18
**/
- uint8_t Profile;
+ UINT8 Profile;
/** Offset 0x004F - MemoryDown
Memory Down. 0x0(Default).
0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4
**/
- uint8_t MemoryDown;
+ UINT8 MemoryDown;
/** Offset 0x0050 - DDR3LPageSize
NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB(Default), 0x02:2KB.
0x1:1KB, 0x2:2KB
**/
- uint8_t DDR3LPageSize;
+ UINT8 DDR3LPageSize;
/** Offset 0x0051 - DDR3LASR
NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported.
0x0:Not Supported, 0x1:Supported
**/
- uint8_t DDR3LASR;
+ UINT8 DDR3LASR;
/** Offset 0x0052 - ScramblerSupport
Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default).
$EN_DIS
**/
- uint8_t ScramblerSupport;
+ UINT8 ScramblerSupport;
/** Offset 0x0053 - ChannelHashMask
Channel Hash Mask. 0x00(Default).
**/
- uint16_t ChannelHashMask;
+ UINT16 ChannelHashMask;
/** Offset 0x0055 - SliceHashMask
Slice Hash Mask. 0x00(Default).
**/
- uint16_t SliceHashMask;
+ UINT16 SliceHashMask;
/** Offset 0x0057 - InterleavedMode
Interleaved Mode. 0x00:Disable(Default), 0x02:Enable.
0x0:Disable, 0x2:Enable
**/
- uint8_t InterleavedMode;
+ UINT8 InterleavedMode;
/** Offset 0x0058 - ChannelsSlicesEnable
Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
- uint8_t ChannelsSlicesEnable;
+ UINT8 ChannelsSlicesEnable;
/** Offset 0x0059 - MinRefRate2xEnable
Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default),
0x01:Enable.
$EN_DIS
**/
- uint8_t MinRefRate2xEnable;
+ UINT8 MinRefRate2xEnable;
/** Offset 0x005A - DualRankSupportEnable
Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default).
$EN_DIS
**/
- uint8_t DualRankSupportEnable;
+ UINT8 DualRankSupportEnable;
/** Offset 0x005B - RmtMode
Rank Margin Tool Mode. 0x00(Default).
$EN_DIS
**/
- uint8_t RmtMode;
+ UINT8 RmtMode;
/** Offset 0x005C - MemorySizeLimit
Memory Size Limit: This value is used to restrict the total amount of memory and
the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB,
0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default)
**/
- uint16_t MemorySizeLimit;
+ UINT16 MemorySizeLimit;
/** Offset 0x005E - LowMemoryMaxValue
Low Memory Max Value: This value is used to restrict the amount of memory below
4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400
= 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default).
**/
- uint16_t LowMemoryMaxValue;
+ UINT16 LowMemoryMaxValue;
/** Offset 0x0060 - DisableFastBoot
00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train
of memory.
$EN_DIS
**/
- uint8_t DisableFastBoot;
+ UINT8 DisableFastBoot;
/** Offset 0x0061 - HighMemoryMaxValue
High Memory Max Value: This value is used to restrict the amount of memory above
4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB,
0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default).
**/
- uint16_t HighMemoryMaxValue;
+ UINT16 HighMemoryMaxValue;
/** Offset 0x0063 - DIMM0SPDAddress
DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default).
**/
- uint8_t DIMM0SPDAddress;
+ UINT8 DIMM0SPDAddress;
/** Offset 0x0064 - DIMM1SPDAddress
DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default).
**/
- uint8_t DIMM1SPDAddress;
+ UINT8 DIMM1SPDAddress;
/** Offset 0x0065 - Ch0_RankEnable
NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default).
**/
- uint8_t Ch0_RankEnable;
+ UINT8 Ch0_RankEnable;
/** Offset 0x0066 - Ch0_DeviceWidth
NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default).
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
- uint8_t Ch0_DeviceWidth;
+ UINT8 Ch0_DeviceWidth;
/** Offset 0x0067 - Ch0_DramDensity
NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default).
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
- uint8_t Ch0_DramDensity;
+ UINT8 Ch0_DramDensity;
/** Offset 0x0068 - Ch0_Option
Rank Select Interleaving Enable. See Address Mapping section for full description.
@@ -297,22 +299,22 @@ struct FSP_M_CONFIG {
This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B).
0x03(Default).
**/
- uint8_t Ch0_Option;
+ UINT8 Ch0_Option;
/** Offset 0x0069 - Ch0_OdtConfig
ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG.
**/
- uint8_t Ch0_OdtConfig;
+ UINT8 Ch0_OdtConfig;
/** Offset 0x006A - Ch0_TristateClk1
Parameter used to determine whether to tristate CLK1. 0x00(Default).
**/
- uint8_t Ch0_TristateClk1;
+ UINT8 Ch0_TristateClk1;
/** Offset 0x006B - Ch0_Mode2N
2N Mode. 0x00(Default).
**/
- uint8_t Ch0_Mode2N;
+ UINT8 Ch0_Mode2N;
/** Offset 0x006C - Ch0_OdtLevels
Rank Select Interleaving Enable. See Address Mapping section for full description.
@@ -321,24 +323,24 @@ struct FSP_M_CONFIG {
0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved.
[5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B).
**/
- uint8_t Ch0_OdtLevels;
+ UINT8 Ch0_OdtLevels;
/** Offset 0x006D - Ch1_RankEnable
NOTE: Only for memory down. Set to 1 to enable Ch1 rank.
**/
- uint8_t Ch1_RankEnable;
+ UINT8 Ch1_RankEnable;
/** Offset 0x006E - Ch1_DeviceWidth
NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default).
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
- uint8_t Ch1_DeviceWidth;
+ UINT8 Ch1_DeviceWidth;
/** Offset 0x006F - Ch1_DramDensity
NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default).
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
- uint8_t Ch1_DramDensity;
+ UINT8 Ch1_DramDensity;
/** Offset 0x0070 - Ch1_Option
Rank Select Interleaving Enable. See Address Mapping section for full description.
@@ -348,45 +350,45 @@ struct FSP_M_CONFIG {
[5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB
(B), 0x03(Default).
**/
- uint8_t Ch1_Option;
+ UINT8 Ch1_Option;
/** Offset 0x0071 - Ch1_OdtConfig
ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG.
**/
- uint8_t Ch1_OdtConfig;
+ UINT8 Ch1_OdtConfig;
/** Offset 0x0072 - Ch1_TristateClk1
Parameter used to determine whether to tristate CLK1. 0x00(Default).
**/
- uint8_t Ch1_TristateClk1;
+ UINT8 Ch1_TristateClk1;
/** Offset 0x0073 - Ch1_Mode2N
2N Mode. 0x00(Default).
**/
- uint8_t Ch1_Mode2N;
+ UINT8 Ch1_Mode2N;
/** Offset 0x0074 - Ch1_OdtLevels
Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default),
1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW.
**/
- uint8_t Ch1_OdtLevels;
+ UINT8 Ch1_OdtLevels;
/** Offset 0x0075 - Ch2_RankEnable
NOTE: Only for memory down. Set to 1 to enable Ch2 rank.
**/
- uint8_t Ch2_RankEnable;
+ UINT8 Ch2_RankEnable;
/** Offset 0x0076 - Ch2_DeviceWidth
NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1.
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
- uint8_t Ch2_DeviceWidth;
+ UINT8 Ch2_DeviceWidth;
/** Offset 0x0077 - Ch2_DramDensity
NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default).
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
- uint8_t Ch2_DramDensity;
+ UINT8 Ch2_DramDensity;
/** Offset 0x0078 - Ch2_Option
Rank Select Interleaving Enable. See Address Mapping section for full description..
@@ -396,47 +398,47 @@ struct FSP_M_CONFIG {
[5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default).
01:2KB (B).
**/
- uint8_t Ch2_Option;
+ UINT8 Ch2_Option;
/** Offset 0x0079 - Ch2_OdtConfig
ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG.
**/
- uint8_t Ch2_OdtConfig;
+ UINT8 Ch2_OdtConfig;
/** Offset 0x007A - Ch2_TristateClk1
Parameter used to determine whether to tristate CLK1. 0x00(Default).
**/
- uint8_t Ch2_TristateClk1;
+ UINT8 Ch2_TristateClk1;
/** Offset 0x007B - Ch2_Mode2N
2N Mode. 0x00(Default).
**/
- uint8_t Ch2_Mode2N;
+ UINT8 Ch2_Mode2N;
/** Offset 0x007C - Ch2_OdtLevels
Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default),
1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW.
**/
- uint8_t Ch2_OdtLevels;
+ UINT8 Ch2_OdtLevels;
/** Offset 0x007D - Ch3_RankEnable
NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default).
**/
- uint8_t Ch3_RankEnable;
+ UINT8 Ch3_RankEnable;
/** Offset 0x007E - Ch3_DeviceWidth
NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default),
0x01:x16, 0x02:x32, 0x03:x64.
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
- uint8_t Ch3_DeviceWidth;
+ UINT8 Ch3_DeviceWidth;
/** Offset 0x007F - Ch3_DramDensity
NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default),
0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb.
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
- uint8_t Ch3_DramDensity;
+ UINT8 Ch3_DramDensity;
/** Offset 0x0080 - Ch3_Option
Rank Select Interleaving Enable. See Address Mapping section for full description..
@@ -446,272 +448,274 @@ struct FSP_M_CONFIG {
[5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01
- 2KB (B).
**/
- uint8_t Ch3_Option;
+ UINT8 Ch3_Option;
/** Offset 0x0081 - Ch3_OdtConfig
ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG.
**/
- uint8_t Ch3_OdtConfig;
+ UINT8 Ch3_OdtConfig;
/** Offset 0x0082 - Ch3_TristateClk1
Parameter used to determine whether to tristate CLK1. 0x00(Default).
**/
- uint8_t Ch3_TristateClk1;
+ UINT8 Ch3_TristateClk1;
/** Offset 0x0083 - Ch3_Mode2N
2N Mode. 0x00(Default).
**/
- uint8_t Ch3_Mode2N;
+ UINT8 Ch3_Mode2N;
/** Offset 0x0084 - Ch3_OdtLevels
Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default),
1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW.
**/
- uint8_t Ch3_OdtLevels;
+ UINT8 Ch3_OdtLevels;
/** Offset 0x0085 - RmtCheckRun
RmtCheckRun: 0x00(Default).
**/
- uint8_t RmtCheckRun;
+ UINT8 RmtCheckRun;
/** Offset 0x0086 - Ch0_Bit_swizzling
Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
- uint8_t Ch0_Bit_swizzling[32];
+ UINT8 Ch0_Bit_swizzling[32];
/** Offset 0x00A6 - Ch1_Bit_swizzling
Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
- uint8_t Ch1_Bit_swizzling[32];
+ UINT8 Ch1_Bit_swizzling[32];
/** Offset 0x00C6 - Ch2_Bit_swizzling
Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
- uint8_t Ch2_Bit_swizzling[32];
+ UINT8 Ch2_Bit_swizzling[32];
/** Offset 0x00E6 - Ch3_Bit_swizzling
Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
- uint8_t Ch3_Bit_swizzling[32];
+ UINT8 Ch3_Bit_swizzling[32];
/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold
RmtMarginCheckScaleHighThreshold. 0x0000(Default).
**/
- uint16_t RmtMarginCheckScaleHighThreshold;
+ UINT16 RmtMarginCheckScaleHighThreshold;
/** Offset 0x0108 - MsgLevelMask
MsgLevelMask. 0x00000000(Default).
**/
- uint32_t MsgLevelMask;
+ UINT32 MsgLevelMask;
/** Offset 0x010C
**/
- uint32_t UnusedUpdSpace0;
+ UINT32 UnusedUpdSpace0;
/** Offset 0x0110 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4
Number of Entries in PreMem GPIO Table. 0(Default).
**/
- uint8_t PreMemGpioTableEntryNum;
+ UINT8 PreMemGpioTableEntryNum;
/** Offset 0x0111 - PreMem GPIO Pin Number for each table
Number of Pins in each PreMem GPIO Table. 0(Default).
**/
- uint8_t PreMemGpioTablePinNum[4];
+ UINT8 PreMemGpioTablePinNum[4];
/** Offset 0x0115 - PreMem GPIO Table Pointer
Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default).
**/
- uint32_t PreMemGpioTablePtr;
+ UINT32 PreMemGpioTablePtr;
/** Offset 0x0119 - Enhance the port 8xh decoding
Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t EnhancePort8xhDecoding;
+ UINT8 EnhancePort8xhDecoding;
/** Offset 0x011A - OEM File Loading Address
Determine the memory base address to load a specified file from CSE file system
after memory is available.
**/
- uint32_t OemLoadingBase;
+ UINT32 OemLoadingBase;
/** Offset 0x011E - OEM File Name to Load
Specify a file name to load from CSE file system after memory is available. Empty
indicates no file needs to be loaded.
**/
- uint8_t OemFileName[16];
+ UINT8 OemFileName[16];
/** Offset 0x012E - SPD Data Write
Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
- uint8_t SpdWriteEnable;
+ UINT8 SpdWriteEnable;
/** Offset 0x012F - MRC Training Data Saving
Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
- uint8_t MrcDataSaving;
+ UINT8 MrcDataSaving;
/** Offset 0x0130 - eMMC Trace Length
Select eMMC trace length to load OEM file from when loading OEM file name is specified.
0x0:Long(Default), 0x1:Short.
0x0:Long, 0x1:Short
**/
- uint8_t eMMCTraceLen;
+ UINT8 eMMCTraceLen;
/** Offset 0x0131
**/
- void* MrcBootDataPtr;
+ VOID* MrcBootDataPtr;
/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB
Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of
CSE. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
- uint8_t SkipCseRbp;
+ UINT8 SkipCseRbp;
/** Offset 0x0136 - Npk Enable
Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default).
0:Disable, 1:Enable, 2:Debugger, 3:Auto
**/
- uint8_t NpkEn;
+ UINT8 NpkEn;
/** Offset 0x0137 - FW Trace Enable
Enable/Disable FW Trace. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t FwTraceEn;
+ UINT8 FwTraceEn;
/** Offset 0x0138 - FW Trace Destination
FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB,
4-NPK_TRACE_TO_PTI(Default).
**/
- uint8_t FwTraceDestination;
+ UINT8 FwTraceDestination;
/** Offset 0x0139 - NPK Recovery Dump
Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t RecoverDump;
+ UINT8 RecoverDump;
/** Offset 0x013A - Memory Region 0 Buffer WrapAround
- Memory Region 0 Buffer WrapAround. 0-n0-wrap, 1-warp(Default).
+ Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
**/
- uint8_t Msc0Wrap;
+ UINT8 Msc0Wrap;
/** Offset 0x013B - Memory Region 1 Buffer WrapAround
Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
**/
- uint8_t Msc1Wrap;
+ UINT8 Msc1Wrap;
/** Offset 0x013C - Memory Region 0 Buffer Size
Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
6-512MB, 7-1GB.
**/
- uint32_t Msc0Size;
+ UINT32 Msc0Size;
/** Offset 0x0140 - Memory Region 1 Buffer Size
Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
6-512MB, 7-1GB.
**/
- uint32_t Msc1Size;
+ UINT32 Msc1Size;
/** Offset 0x0144 - PTI Mode
PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16.
**/
- uint8_t PtiMode;
+ UINT8 PtiMode;
/** Offset 0x0145 - PTI Training
PTI Training. 0-off(Default), 1-6=1-6.
**/
- uint8_t PtiTraining;
+ UINT8 PtiTraining;
/** Offset 0x0146 - PTI Speed
PTI Speed. 0-full, 1-half, 2-quarter(Default).
**/
- uint8_t PtiSpeed;
+ UINT8 PtiSpeed;
/** Offset 0x0147 - Punit Message Level
Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
**/
- uint8_t PunitMlvl;
+ UINT8 PunitMlvl;
/** Offset 0x0148 - PMC Message Level
PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
**/
- uint8_t PmcMlvl;
+ UINT8 PmcMlvl;
/** Offset 0x0149 - SW Trace Enable
Enable/Disable SW Trace. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t SwTraceEn;
+ UINT8 SwTraceEn;
/** Offset 0x014A - Periodic Retraining Disable
Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
- uint8_t PeriodicRetrainingDisable;
+ UINT8 PeriodicRetrainingDisable;
/** Offset 0x014B
**/
- uint8_t ReservedFspmUpd[5];
-} __attribute__((packed));
+ UINT8 ReservedFspmUpd[5];
+} FSP_M_CONFIG;
/** Fsp M Test Configuration
**/
-struct FSP_M_TEST_CONFIG {
+typedef struct {
/** Offset 0x0150
**/
- uint32_t Signature;
+ UINT32 Signature;
/** Offset 0x0154
**/
- uint8_t ReservedFspmTestUpd[28];
-} __attribute__((packed));
+ UINT8 ReservedFspmTestUpd[28];
+} FSP_M_TEST_CONFIG;
/** Fsp M Restricted Configuration
**/
-struct FSP_M_RESTRICTED_CONFIG {
+typedef struct {
/** Offset 0x0170
**/
- uint32_t Signature;
+ UINT32 Signature;
/** Offset 0x0174
**/
- uint8_t ReservedFspmRestrictedUpd[138];
-} __attribute__((packed));
+ UINT8 ReservedFspmRestrictedUpd[138];
+} FSP_M_RESTRICTED_CONFIG;
/** Fsp M UPD Configuration
**/
-struct FSPM_UPD {
+typedef struct {
/** Offset 0x0000
**/
- struct FSP_UPD_HEADER FspUpdHeader;
+ FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
- struct FSPM_ARCH_UPD FspmArchUpd;
+ FSPM_ARCH_UPD FspmArchUpd;
/** Offset 0x0040
**/
- struct FSP_M_CONFIG FspmConfig;
+ FSP_M_CONFIG FspmConfig;
/** Offset 0x0150
**/
- struct FSP_M_TEST_CONFIG FspmTestConfig;
+ FSP_M_TEST_CONFIG FspmTestConfig;
/** Offset 0x0170
**/
- struct FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;
+ FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;
/** Offset 0x01FE
**/
- uint16_t UpdTerminator;
-} __attribute__((packed));
+ UINT16 UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack(pop)
#endif
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
index 26f70a7bbd..553eba3f18 100644
--- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
+++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
@@ -33,516 +33,518 @@ are permitted provided that the following conditions are met:
#ifndef __FSPSUPD_H__
#define __FSPSUPD_H__
-#include "FspUpd.h"
-#include <fsp/upd.h>
+#include <FspUpd.h>
+
+#pragma pack(push, 1)
+
/** Fsp S Configuration
**/
-struct FSP_S_CONFIG {
+typedef struct {
/** Offset 0x0020 - ActiveProcessorCores
Number of active cores. 0:Disable(Default), 1:Enable.
**/
- uint8_t ActiveProcessorCores;
+ UINT8 ActiveProcessorCores;
/** Offset 0x0021 - Disable Core1
Disable/Enable Core1. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t DisableCore1;
+ UINT8 DisableCore1;
/** Offset 0x0022 - Disable Core2
Disable/Enable Core2. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t DisableCore2;
+ UINT8 DisableCore2;
/** Offset 0x0023 - Disable Core3
Disable/Enable Core3. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t DisableCore3;
+ UINT8 DisableCore3;
/** Offset 0x0024 - VMX Enable
Enable or Disable VMX. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t VmxEnable;
+ UINT8 VmxEnable;
/** Offset 0x0025 - Memory region allocation for Processor Trace
Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to
128MB (0xF); <b>0xFF: Disable. 0xFF:Disable(Default)
**/
- uint8_t ProcTraceMemSize;
+ UINT8 ProcTraceMemSize;
/** Offset 0x0026 - Enable Processor Trace
Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t ProcTraceEnable;
+ UINT8 ProcTraceEnable;
/** Offset 0x0027 - Eist
Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t Eist;
+ UINT8 Eist;
/** Offset 0x0028 - Boot PState
Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM.
**/
- uint8_t BootPState;
+ UINT8 BootPState;
/** Offset 0x0029 - CPU power states (C-states)
Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t EnableCx;
+ UINT8 EnableCx;
/** Offset 0x002A - Enhanced C-states
Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t C1e;
+ UINT8 C1e;
/** Offset 0x002B - Bi-Directional PROCHOT#
Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t BiProcHot;
+ UINT8 BiProcHot;
/** Offset 0x002C - Max Pkg Cstate
Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s,
6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto.
**/
- uint8_t PkgCStateLimit;
+ UINT8 PkgCStateLimit;
/** Offset 0x002D
**/
- uint8_t UnusedUpdSpace0;
+ UINT8 UnusedUpdSpace0;
/** Offset 0x002E - C-State auto-demotion
C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7
Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion
to C1 and C3.
**/
- uint8_t CStateAutoDemotion;
+ UINT8 CStateAutoDemotion;
/** Offset 0x002F - C-State un-demotion
C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion,
2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion.
**/
- uint8_t CStateUnDemotion;
+ UINT8 CStateUnDemotion;
/** Offset 0x0030 - Max Core C-State
Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default).
**/
- uint8_t MaxCoreCState;
+ UINT8 MaxCoreCState;
/** Offset 0x0031 - Package C-State Demotion
Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t PkgCStateDemotion;
+ UINT8 PkgCStateDemotion;
/** Offset 0x0032 - Package C-State Un-demotion
Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t PkgCStateUnDemotion;
+ UINT8 PkgCStateUnDemotion;
/** Offset 0x0033 - Turbo Mode
Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t TurboMode;
+ UINT8 TurboMode;
/** Offset 0x0034 - SC HDA Verb Table Entry Number
Number of Entries in Verb Table. 0(Default).
**/
- uint8_t HdaVerbTableEntryNum;
+ UINT8 HdaVerbTableEntryNum;
/** Offset 0x0035 - SC HDA Verb Table Pointer
Pointer to Array of pointers to Verb Table. 0x00000000(Default).
**/
- uint32_t HdaVerbTablePtr;
+ UINT32 HdaVerbTablePtr;
/** Offset 0x0039 - Enable/Disable P2SB device hidden.
Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t P2sbUnhide;
+ UINT8 P2sbUnhide;
/** Offset 0x003A - IPU Enable/Disable
Enable/Disable IPU Device. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t IpuEn;
+ UINT8 IpuEn;
/** Offset 0x003B - IMGU ACPI mode selection
0:Auto, 1:IGFX Child device(Default), 2:ACPI device.
0:Disable, 1:IGFX Child device, 2:ACPI device
**/
- uint8_t IpuAcpiMode;
+ UINT8 IpuAcpiMode;
/** Offset 0x003C - GttMmAdr
GttMmAdr structure for initialization. 0xBF000000(Default).
**/
- uint32_t GttMmAdr;
+ UINT32 GttMmAdr;
/** Offset 0x0040 - GmAdr
GmAdr structure for initialization. 0xA0000000(Default).
**/
- uint32_t GmAdr;
+ UINT32 GmAdr;
/** Offset 0x0044 - Enable ForceWake
Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t ForceWake;
+ UINT8 ForceWake;
/** Offset 0x0045 - Enable PavpLock
Enable/disable PavpLock. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t PavpLock;
+ UINT8 PavpLock;
/** Offset 0x0046 - Enable GraphicsFreqModify
Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t GraphicsFreqModify;
+ UINT8 GraphicsFreqModify;
/** Offset 0x0047 - Enable GraphicsFreqReq
Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t GraphicsFreqReq;
+ UINT8 GraphicsFreqReq;
/** Offset 0x0048 - Enable GraphicsVideoFreq
Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t GraphicsVideoFreq;
+ UINT8 GraphicsVideoFreq;
/** Offset 0x0049 - Enable PmLock
Enable/disable PmLock. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t PmLock;
+ UINT8 PmLock;
/** Offset 0x004A - Enable DopClockGating
Enable/disable DopClockGating. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t DopClockGating;
+ UINT8 DopClockGating;
/** Offset 0x004B - Enable UnsolicitedAttackOverride
Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t UnsolicitedAttackOverride;
+ UINT8 UnsolicitedAttackOverride;
/** Offset 0x004C - Enable WOPCMSupport
Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t WOPCMSupport;
+ UINT8 WOPCMSupport;
/** Offset 0x004D - Enable WOPCMSize
Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t WOPCMSize;
+ UINT8 WOPCMSize;
/** Offset 0x004E - Enable PowerGating
Enable/disable PowerGating. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t PowerGating;
+ UINT8 PowerGating;
/** Offset 0x004F - Enable UnitLevelClockGating
Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t UnitLevelClockGating;
+ UINT8 UnitLevelClockGating;
/** Offset 0x0050 - Enable FastBoot
Enable/disable FastBoot. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t FastBoot;
+ UINT8 FastBoot;
/** Offset 0x0051 - Enable DynSR
Enable/disable DynSR. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t DynSR;
+ UINT8 DynSR;
/** Offset 0x0052 - Enable SaIpuEnable
Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t SaIpuEnable;
+ UINT8 SaIpuEnable;
/** Offset 0x0053 - BMP Logo Data Size
BMP logo data buffer size. 0x00000000(Default).
**/
- uint32_t LogoSize;
+ UINT32 LogoSize;
/** Offset 0x0057 - BMP Logo Data Pointer
BMP logo data pointer to a BMP format buffer. 0x00000000(Default).
**/
- uint32_t LogoPtr;
+ UINT32 LogoPtr;
/** Offset 0x005B - Graphics Configuration Data Pointer
Graphics configuration data used for initialization. 0x00000000(Default).
**/
- uint32_t GraphicsConfigPtr;
+ UINT32 GraphicsConfigPtr;
/** Offset 0x005F - GT PM Support
Enable/Disable GT power management support. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t PmSupport;
+ UINT8 PmSupport;
/** Offset 0x0060 - RC6(Render Standby)
Enable/Disable render standby support. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t EnableRenderStandby;
+ UINT8 EnableRenderStandby;
/** Offset 0x0061 - PAVP Enable
Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t PavpEnable;
+ UINT8 PavpEnable;
/** Offset 0x0062 - PAVP PR3
Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t PavpPr3;
+ UINT8 PavpPr3;
/** Offset 0x0063 - CdClock Frequency selection
0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default).
0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz
**/
- uint8_t CdClock;
+ UINT8 CdClock;
/** Offset 0x0064 - Enable/Disable PeiGraphicsPeimInit
Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t PeiGraphicsPeimInit;
+ UINT8 PeiGraphicsPeimInit;
/** Offset 0x0065 - Write Protection Support
Enable/disable Write Protection. 0:Disable, 1:Enable(Default).
**/
- uint8_t WriteProtectionEnable[5];
+ UINT8 WriteProtectionEnable[5];
/** Offset 0x006A - Read Protection Support
Enable/disable Read Protection. 0:Disable, 1:Enable(Default).
**/
- uint8_t ReadProtectionEnable[5];
+ UINT8 ReadProtectionEnable[5];
/** Offset 0x006F - Protected Range Limitation
The address of the upper limit of protection, 0x0FFFh(Default).
**/
- uint16_t ProtectedRangeLimit[5];
+ UINT16 ProtectedRangeLimit[5];
/** Offset 0x0079 - Protected Range Base
The base address of the upper limit of protection. 0x0000(Default).
**/
- uint16_t ProtectedRangeBase[5];
+ UINT16 ProtectedRangeBase[5];
/** Offset 0x0083 - Enable SC Gaussian Mixture Models
Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t Gmm;
+ UINT8 Gmm;
/** Offset 0x0084 - GMM Clock Gating - PGCB Clock Trunk
Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ClkGatingPgcbClkTrunk;
+ UINT8 ClkGatingPgcbClkTrunk;
/** Offset 0x0085 - GMM Clock Gating - Sideband
Enable/disable Sideband. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ClkGatingSb;
+ UINT8 ClkGatingSb;
/** Offset 0x0086 - GMM Clock Gating - Sideband
Enable/disable Sideband. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ClkGatingSbClkTrunk;
+ UINT8 ClkGatingSbClkTrunk;
/** Offset 0x0087 - GMM Clock Gating - Sideband Clock Partition
Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ClkGatingSbClkPartition;
+ UINT8 ClkGatingSbClkPartition;
/** Offset 0x0088 - GMM Clock Gating - Core
Enable/disable Core. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ClkGatingCore;
+ UINT8 ClkGatingCore;
/** Offset 0x0089 - GMM Clock Gating - DMA
Enable/disable DMA. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ClkGatingDma;
+ UINT8 ClkGatingDma;
/** Offset 0x008A - GMM Clock Gating - Register Access
Enable/disable Register Access. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ClkGatingRegAccess;
+ UINT8 ClkGatingRegAccess;
/** Offset 0x008B - GMM Clock Gating - Host
Enable/disable Host. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ClkGatingHost;
+ UINT8 ClkGatingHost;
/** Offset 0x008C - GMM Clock Gating - Partition
Enable/disable Partition. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ClkGatingPartition;
+ UINT8 ClkGatingPartition;
/** Offset 0x008D - Clock Gating - Trunk
Enable/disable Trunk. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ClkGatingTrunk;
+ UINT8 ClkGatingTrunk;
/** Offset 0x008E - HD Audio Support
Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t HdaEnable;
+ UINT8 HdaEnable;
/** Offset 0x008F - HD Audio DSP Support
Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t DspEnable;
+ UINT8 DspEnable;
/** Offset 0x0090 - Azalia wake-on-ring
Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t Pme;
+ UINT8 Pme;
/** Offset 0x0091 - HD-Audio I/O Buffer Ownership
Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default)
0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and
I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers
**/
- uint8_t HdAudioIoBufferOwnership;
+ UINT8 HdAudioIoBufferOwnership;
/** Offset 0x0092 - HD-Audio I/O Buffer Voltage
HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V.
0: 3.3V, 1: 1.8V
**/
- uint8_t HdAudioIoBufferVoltage;
+ UINT8 HdAudioIoBufferVoltage;
/** Offset 0x0093 - HD-Audio Virtual Channel Type
HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1.
0: VC0, 1: VC1
**/
- uint8_t HdAudioVcType;
+ UINT8 HdAudioVcType;
/** Offset 0x0094 - HD-Audio Link Frequency
HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,
4:96MHz, 5:Invalid.
0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid
**/
- uint8_t HdAudioLinkFrequency;
+ UINT8 HdAudioLinkFrequency;
/** Offset 0x0095 - HD-Audio iDisp-Link Frequency
HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,
4:96MHz, 5:Invalid.
0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid
**/
- uint8_t HdAudioIDispLinkFrequency;
+ UINT8 HdAudioIDispLinkFrequency;
/** Offset 0x0096 - HD-Audio iDisp-Link T-Mode
HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T.
0: 2T, 1: 1T
**/
- uint8_t HdAudioIDispLinkTmode;
+ UINT8 HdAudioIDispLinkTmode;
/** Offset 0x0097 - HD-Audio Disp DMIC
HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array.
0: Disable, 1: 2ch array, 2: 4ch array
**/
- uint8_t DspEndpointDmic;
+ UINT8 DspEndpointDmic;
/** Offset 0x0098 - HD-Audio Bluetooth
Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t DspEndpointBluetooth;
+ UINT8 DspEndpointBluetooth;
/** Offset 0x0099 - HD-Audio I2S SHK
Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t DspEndpointI2sSkp;
+ UINT8 DspEndpointI2sSkp;
/** Offset 0x009A - HD-Audio I2S HP
Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t DspEndpointI2sHp;
+ UINT8 DspEndpointI2sHp;
/** Offset 0x009B - HD-Audio Controller Power Gating
Enable/Disable HD-Audio Controller Power Gating. This option is deprecated.
$EN_DIS
**/
- uint8_t AudioCtlPwrGate;
+ UINT8 AudioCtlPwrGate;
/** Offset 0x009C - HD-Audio ADSP Power Gating
Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated.
$EN_DIS
**/
- uint8_t AudioDspPwrGate;
+ UINT8 AudioDspPwrGate;
/** Offset 0x009D - HD-Audio CSME Memory Transfers
Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2.
0: VC0, 1: VC2
**/
- uint8_t Mmt;
+ UINT8 Mmt;
/** Offset 0x009E - HD-Audio Host Memory Transfers
Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2.
0: VC0, 1: VC2
**/
- uint8_t Hmt;
+ UINT8 Hmt;
/** Offset 0x009F - HD-Audio BIOS Configuration Lock Down
Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t BiosCfgLockDown;
+ UINT8 BiosCfgLockDown;
/** Offset 0x00A0 - HD-Audio Power Gating
Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t HDAudioPwrGate;
+ UINT8 HDAudioPwrGate;
/** Offset 0x00A1 - HD-Audio Clock Gatingn
Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t HDAudioClkGate;
+ UINT8 HDAudioClkGate;
/** Offset 0x00A2 - Bitmask of DSP Feature
Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default).
@@ -550,7 +552,7 @@ struct FSP_S_CONFIG {
- BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:
Intel WoV, 1: Windows Voice Activation
**/
- uint32_t DspFeatureMask;
+ UINT32 DspFeatureMask;
/** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules
Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default).
@@ -558,726 +560,726 @@ struct FSP_S_CONFIG {
- BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:
Intel WoV, 1: Windows Voice Activation
**/
- uint32_t DspPpModuleMask;
+ UINT32 DspPpModuleMask;
/** Offset 0x00AA - Enable High Precision Timer
Enable/Disable Hpet. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t Hpet;
+ UINT8 Hpet;
/** Offset 0x00AB - Hpet Valid BDF Value
Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t HpetBdfValid;
+ UINT8 HpetBdfValid;
/** Offset 0x00AC - Bus Number of Hpet
Completer ID of Bus Number of Hpet. Default = 0xFA(Default).
**/
- uint8_t HpetBusNumber;
+ UINT8 HpetBusNumber;
/** Offset 0x00AD - Device Number of Hpet
Completer ID of Device Number of Hpet. 0x1F(Default).
**/
- uint8_t HpetDeviceNumber;
+ UINT8 HpetDeviceNumber;
/** Offset 0x00AE - Function Number of Hpet
Completer ID of Function Number of Hpet. 0x00(Default).
**/
- uint8_t HpetFunctionNumber;
+ UINT8 HpetFunctionNumber;
/** Offset 0x00AF
**/
- uint32_t UnusedUpdSpace1;
+ UINT32 UnusedUpdSpace1;
/** Offset 0x00B3 - IoApic Valid BDF Value
Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t IoApicBdfValid;
+ UINT8 IoApicBdfValid;
/** Offset 0x00B4 - Bus Number of IoApic
Completer ID of Bus Number of IoApic. 0xFA(Default).
**/
- uint8_t IoApicBusNumber;
+ UINT8 IoApicBusNumber;
/** Offset 0x00B5 - Device Number of IoApic
Completer ID of Device Number of IoApic. 0x0F(Default).
**/
- uint8_t IoApicDeviceNumber;
+ UINT8 IoApicDeviceNumber;
/** Offset 0x00B6 - Function Number of IoApic
Completer ID of Function Number of IoApic. 0x00(Default).
**/
- uint8_t IoApicFunctionNumber;
+ UINT8 IoApicFunctionNumber;
/** Offset 0x00B7 - IOAPIC Entry 24-119
Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t IoApicEntry24_119;
+ UINT8 IoApicEntry24_119;
/** Offset 0x00B8 - IO APIC ID
This member determines IOAPIC ID. 0x01(Default).
**/
- uint8_t IoApicId;
+ UINT8 IoApicId;
/** Offset 0x00B9 - IoApic Range
Define address bits 19:12 for the IOxAPIC range. 0x00(Default).
**/
- uint8_t IoApicRangeSelect;
+ UINT8 IoApicRangeSelect;
/** Offset 0x00BA - ISH Controller
Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t IshEnable;
+ UINT8 IshEnable;
/** Offset 0x00BB - BIOS Interface Lock Down
Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control
Register. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t BiosInterface;
+ UINT8 BiosInterface;
/** Offset 0x00BC - Bios LockDown Enable
Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t BiosLock;
+ UINT8 BiosLock;
/** Offset 0x00BD - SPI EISS Status
Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t SpiEiss;
+ UINT8 SpiEiss;
/** Offset 0x00BE - BiosLock SWSMI Number
This member describes the SwSmi value for Bios Lock. 0xA9(Default).
**/
- uint8_t BiosLockSwSmiNumber;
+ UINT8 BiosLockSwSmiNumber;
/** Offset 0x00BF - LPSS IOSF PMCTL S0ix Enable
Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t LPSS_S0ixEnable;
+ UINT8 LPSS_S0ixEnable;
/** Offset 0x00C0 - LPSS I2C Clock Gating Configuration
Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default).
**/
- uint8_t I2cClkGateCfg[8];
+ UINT8 I2cClkGateCfg[8];
/** Offset 0x00C8 - PSS HSUART Clock Gating Configuration
Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default).
**/
- uint8_t HsuartClkGateCfg[4];
+ UINT8 HsuartClkGateCfg[4];
/** Offset 0x00CC - LPSS SPI Clock Gating Configuration
Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default).
**/
- uint8_t SpiClkGateCfg[3];
+ UINT8 SpiClkGateCfg[3];
/** Offset 0x00CF - I2C Device 0
Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t I2c0Enable;
+ UINT8 I2c0Enable;
/** Offset 0x00D0 - I2C Device 1
Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t I2c1Enable;
+ UINT8 I2c1Enable;
/** Offset 0x00D1 - I2C Device 2
Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t I2c2Enable;
+ UINT8 I2c2Enable;
/** Offset 0x00D2 - I2C Device 3
Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t I2c3Enable;
+ UINT8 I2c3Enable;
/** Offset 0x00D3 - I2C Device 4
Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t I2c4Enable;
+ UINT8 I2c4Enable;
/** Offset 0x00D4 - I2C Device 5
Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t I2c5Enable;
+ UINT8 I2c5Enable;
/** Offset 0x00D5 - I2C Device 6
Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t I2c6Enable;
+ UINT8 I2c6Enable;
/** Offset 0x00D6 - I2C Device 7
Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t I2c7Enable;
+ UINT8 I2c7Enable;
/** Offset 0x00D7 - UART Device 0
Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t Hsuart0Enable;
+ UINT8 Hsuart0Enable;
/** Offset 0x00D8 - UART Device 1
Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t Hsuart1Enable;
+ UINT8 Hsuart1Enable;
/** Offset 0x00D9 - UART Device 2
Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t Hsuart2Enable;
+ UINT8 Hsuart2Enable;
/** Offset 0x00DA - UART Device 3
Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t Hsuart3Enable;
+ UINT8 Hsuart3Enable;
/** Offset 0x00DB - SPI UART Device 0
Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t Spi0Enable;
+ UINT8 Spi0Enable;
/** Offset 0x00DC - SPI UART Device 1
Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t Spi1Enable;
+ UINT8 Spi1Enable;
/** Offset 0x00DD - SPI UART Device 2
Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
0: Disabled, 1: PCI Mode, 2: ACPI Mode
**/
- uint8_t Spi2Enable;
+ UINT8 Spi2Enable;
/** Offset 0x00DE - UART Debug Base Address
UART Debug Base Address. 0x00000000(Default).
**/
- uint32_t Uart2KernelDebugBaseAddress;
+ UINT32 Uart2KernelDebugBaseAddress;
/** Offset 0x00E2 - OS Debug Feature
Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable.
$EN_DIS
**/
- uint8_t OsDbgEnable;
+ UINT8 OsDbgEnable;
/** Offset 0x00E3 - DCI Feature
Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable.
$EN_DIS
**/
- uint8_t DciEn;
+ UINT8 DciEn;
/** Offset 0x00E4 - Enable PCIE Clock Gating
Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default).
0:Enable, 1:Disable
**/
- uint8_t PcieClockGatingDisabled;
+ UINT8 PcieClockGatingDisabled;
/** Offset 0x00E5 - Enable PCIE Root Port 8xh Decode
Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t PcieRootPort8xhDecode;
+ UINT8 PcieRootPort8xhDecode;
/** Offset 0x00E6 - PCIE 8xh Decode Port Index
PCIE 8xh Decode Port Index. 0x00(Default).
**/
- uint8_t Pcie8xhDecodePortIndex;
+ UINT8 Pcie8xhDecodePortIndex;
/** Offset 0x00E7 - Enable PCIE Root Port Peer Memory Write
Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t PcieRootPortPeerMemoryWriteEnable;
+ UINT8 PcieRootPortPeerMemoryWriteEnable;
/** Offset 0x00E8 - PCIE SWSMI Number
This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default).
**/
- uint8_t PcieAspmSwSmiNumber;
+ UINT8 PcieAspmSwSmiNumber;
/** Offset 0x00E9 - PCI Express Root Port
Control the PCI Express Root Port . 0:Disable, 1:Enable(Default).
**/
- uint8_t PcieRootPortEn[6];
+ UINT8 PcieRootPortEn[6];
/** Offset 0x00EF - Hide PCIE Root Port Configuration Space
Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable.
**/
- uint8_t PcieRpHide[6];
+ UINT8 PcieRpHide[6];
/** Offset 0x00F5 - PCIE Root Port Slot Implement
Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default).
**/
- uint8_t PcieRpSlotImplemented[6];
+ UINT8 PcieRpSlotImplemented[6];
/** Offset 0x00FB - Hot Plug
PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default).
**/
- uint8_t PcieRpHotPlug[6];
+ UINT8 PcieRpHotPlug[6];
/** Offset 0x0101 - PCIE PM SCI
Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable.
**/
- uint8_t PcieRpPmSci[6];
+ UINT8 PcieRpPmSci[6];
/** Offset 0x0107 - PCIE Root Port Extended Sync
Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default).
**/
- uint8_t PcieRpExtSync[6];
+ UINT8 PcieRpExtSync[6];
/** Offset 0x010D - Transmitter Half Swing
Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default).
**/
- uint8_t PcieRpTransmitterHalfSwing[6];
+ UINT8 PcieRpTransmitterHalfSwing[6];
/** Offset 0x0113 - ACS
Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default).
**/
- uint8_t PcieRpAcsEnabled[6];
+ UINT8 PcieRpAcsEnabled[6];
/** Offset 0x0119 - Clock Request Support
Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default).
**/
- uint8_t PcieRpClkReqSupported[6];
+ UINT8 PcieRpClkReqSupported[6];
/** Offset 0x011F - Configure CLKREQ Number
Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00,
0x01, 0x02, 0x03.
**/
- uint8_t PcieRpClkReqNumber[6];
+ UINT8 PcieRpClkReqNumber[6];
/** Offset 0x0125 - CLKREQ# Detection
Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable.
**/
- uint8_t PcieRpClkReqDetect[6];
+ UINT8 PcieRpClkReqDetect[6];
/** Offset 0x012B - Advanced Error Reporting
Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable.
**/
- uint8_t AdvancedErrorReporting[6];
+ UINT8 AdvancedErrorReporting[6];
/** Offset 0x0131 - PME Interrupt
Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable.
**/
- uint8_t PmeInterrupt[6];
+ UINT8 PmeInterrupt[6];
/** Offset 0x0137 - URR
PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
**/
- uint8_t UnsupportedRequestReport[6];
+ UINT8 UnsupportedRequestReport[6];
/** Offset 0x013D - FER
PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
**/
- uint8_t FatalErrorReport[6];
+ UINT8 FatalErrorReport[6];
/** Offset 0x0143 - NFER
PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
**/
- uint8_t NoFatalErrorReport[6];
+ UINT8 NoFatalErrorReport[6];
/** Offset 0x0149 - CER
PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
**/
- uint8_t CorrectableErrorReport[6];
+ UINT8 CorrectableErrorReport[6];
/** Offset 0x014F - SEFE
Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.
**/
- uint8_t SystemErrorOnFatalError[6];
+ UINT8 SystemErrorOnFatalError[6];
/** Offset 0x0155 - SENFE
Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.
**/
- uint8_t SystemErrorOnNonFatalError[6];
+ UINT8 SystemErrorOnNonFatalError[6];
/** Offset 0x015B - SECE
Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable.
**/
- uint8_t SystemErrorOnCorrectableError[6];
+ UINT8 SystemErrorOnCorrectableError[6];
/** Offset 0x0161 - PCIe Speed
Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3.
**/
- uint8_t PcieRpSpeed[6];
+ UINT8 PcieRpSpeed[6];
/** Offset 0x0167 - Physical Slot Number
Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05.
**/
- uint8_t PhysicalSlotNumber[6];
+ UINT8 PhysicalSlotNumber[6];
/** Offset 0x016D - CTO
Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable.
**/
- uint8_t PcieRpCompletionTimeout[6];
+ UINT8 PcieRpCompletionTimeout[6];
/** Offset 0x0173 - PTM Support
Enable/Disable PTM Support. 0:Disable(Default), 1:Enable.
**/
- uint8_t PtmEnable[6];
+ UINT8 PtmEnable[6];
/** Offset 0x0179 - ASPM
PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1,
4:Auto(Default).
**/
- uint8_t PcieRpAspm[6];
+ UINT8 PcieRpAspm[6];
/** Offset 0x017F - L1 Substates
PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default).
**/
- uint8_t PcieRpL1Substates[6];
+ UINT8 PcieRpL1Substates[6];
/** Offset 0x0185 - PCH PCIe LTR
PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default).
**/
- uint8_t PcieRpLtrEnable[6];
+ UINT8 PcieRpLtrEnable[6];
/** Offset 0x018B - PCIE LTR Lock
PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable.
**/
- uint8_t PcieRpLtrConfigLock[6];
+ UINT8 PcieRpLtrConfigLock[6];
/** Offset 0x0191 - PME_B0_S5 Disable bit
PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t PmeB0S5Dis;
+ UINT8 PmeB0S5Dis;
/** Offset 0x0192 - PCI Clock Run
This member describes whether or not the PCI ClockRun feature of SC should be enabled.
0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t PciClockRun;
+ UINT8 PciClockRun;
/** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting
Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t Timer8254ClkSetting;
+ UINT8 Timer8254ClkSetting;
/** Offset 0x0194 - Chipset SATA
Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports
the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t EnableSata;
+ UINT8 EnableSata;
/** Offset 0x0195 - SATA Mode Selection
Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID.
0:AHCI, 1:RAID
**/
- uint8_t SataMode;
+ UINT8 SataMode;
/** Offset 0x0196 - Aggressive LPM Support
Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t SataSalpSupport;
+ UINT8 SataSalpSupport;
/** Offset 0x0197 - SATA Power Optimization
Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t SataPwrOptEnable;
+ UINT8 SataPwrOptEnable;
/** Offset 0x0198 - eSATA Speed Limit
Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t eSATASpeedLimit;
+ UINT8 eSATASpeedLimit;
/** Offset 0x0199 - SATA Speed Limit
SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3).
0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1)
**/
- uint8_t SpeedLimit;
+ UINT8 SpeedLimit;
/** Offset 0x019A - SATA Port
Enable or Disable SATA Port. 0:Disable, 1:Enable(Default).
**/
- uint8_t SataPortsEnable[2];
+ UINT8 SataPortsEnable[2];
/** Offset 0x019C - SATA Port DevSlp
Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable.
**/
- uint8_t SataPortsDevSlp[2];
+ UINT8 SataPortsDevSlp[2];
/** Offset 0x019E - SATA Port HotPlug
Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable.
**/
- uint8_t SataPortsHotPlug[2];
+ UINT8 SataPortsHotPlug[2];
/** Offset 0x01A0 - Mechanical Presence Switch
Controls reporting if this port has an Mechanical Presence Switch.\n
Note:Requires hardware support. 0:Disable, 1:Enable(Default).
**/
- uint8_t SataPortsInterlockSw[2];
+ UINT8 SataPortsInterlockSw[2];
/** Offset 0x01A2 - External SATA Ports
Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable.
**/
- uint8_t SataPortsExternal[2];
+ UINT8 SataPortsExternal[2];
/** Offset 0x01A4 - Spin Up Device
Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable.
**/
- uint8_t SataPortsSpinUp[2];
+ UINT8 SataPortsSpinUp[2];
/** Offset 0x01A6 - SATA Solid State
Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard
Disk Drive(Default), 1:Solid State Drive.
**/
- uint8_t SataPortsSolidStateDrive[2];
+ UINT8 SataPortsSolidStateDrive[2];
/** Offset 0x01A8 - DITO Configuration
Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable.
**/
- uint8_t SataPortsEnableDitoConfig[2];
+ UINT8 SataPortsEnableDitoConfig[2];
/** Offset 0x01AA - DM Value
DM Value. 0:Minimum, 0x0F:Maximum(Default).
**/
- uint8_t SataPortsDmVal[2];
+ UINT8 SataPortsDmVal[2];
/** Offset 0x01AC - DITO Value
DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default).
**/
- uint16_t SataPortsDitoVal[2];
+ UINT16 SataPortsDitoVal[2];
/** Offset 0x01B0 - Subsystem Vendor ID
Subsystem Vendor ID. 0x8086(Default).
**/
- uint16_t SubSystemVendorId;
+ UINT16 SubSystemVendorId;
/** Offset 0x01B2 - Subsystem ID
Subsystem ID. 0x7270(Default).
**/
- uint16_t SubSystemId;
+ UINT16 SubSystemId;
/** Offset 0x01B4
**/
- uint8_t UnusedUpdSpace2[10];
+ UINT8 UnusedUpdSpace2[10];
/** Offset 0x01BE - CRIDSettings
PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3.
**/
- uint8_t CRIDSettings;
+ UINT8 CRIDSettings;
/** Offset 0x01BF - ResetSelect
ResetSelect. 0x6:warm reset(Default), 0xE:cold reset.
**/
- uint8_t ResetSelect;
+ UINT8 ResetSelect;
/** Offset 0x01C0 - SD Card Support (D27:F0)
Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t SdcardEnabled;
+ UINT8 SdcardEnabled;
/** Offset 0x01C1 - SeMMC Support (D28:F0)
Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t eMMCEnabled;
+ UINT8 eMMCEnabled;
/** Offset 0x01C2 - eMMC Max Speed
Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50.
0:HS400, 1: HS200, 2:DDR50
**/
- uint8_t eMMCHostMaxSpeed;
+ UINT8 eMMCHostMaxSpeed;
/** Offset 0x01C3 - UFS Support (D29:F0)
Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t UfsEnabled;
+ UINT8 UfsEnabled;
/** Offset 0x01C4 - SDIO Support (D30:F0)
Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t SdioEnabled;
+ UINT8 SdioEnabled;
/** Offset 0x01C5 - GPP Lock Feature
Enable/Disable GPP lock. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t GppLock;
+ UINT8 GppLock;
/** Offset 0x01C6 - Serial IRQ
Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t SirqEnable;
+ UINT8 SirqEnable;
/** Offset 0x01C7 - Serial IRQ Mode
Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode.
$EN_DIS
**/
- uint8_t SirqMode;
+ UINT8 SirqMode;
/** Offset 0x01C8 - Start Frame Pulse Width
Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk.
0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk
**/
- uint8_t StartFramePulse;
+ UINT8 StartFramePulse;
/** Offset 0x01C9 - Enable SMBus
Enable/disable SMBus controller. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t SmbusEnable;
+ UINT8 SmbusEnable;
/** Offset 0x01CA - SMBus ARP Support
Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t ArpEnable;
+ UINT8 ArpEnable;
/** Offset 0x01CB
**/
- uint16_t UnusedUpdSpace3;
+ UINT16 UnusedUpdSpace3;
/** Offset 0x01CD - SMBus Table Elements
The number of elements in the Reserved SMBus Address Table. 0x0080(Default).
**/
- uint16_t NumRsvdSmbusAddresses;
+ UINT16 NumRsvdSmbusAddresses;
/** Offset 0x01CF - Reserved SMBus Address Table
Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default).
**/
- uint8_t RsvdSmbusAddressTable[128];
+ UINT8 RsvdSmbusAddressTable[128];
/** Offset 0x024F - XHCI Disable Compliance Mode
Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance
Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True.
$EN_DIS
**/
- uint8_t DisableComplianceMode;
+ UINT8 DisableComplianceMode;
/** Offset 0x0250 - USB Per-Port Control
Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t UsbPerPortCtl;
+ UINT8 UsbPerPortCtl;
/** Offset 0x0251 - xHCI Mode
Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default)
0:Disable, 1:Enable, 2:Auto
**/
- uint8_t Usb30Mode;
+ UINT8 Usb30Mode;
/** Offset 0x0252 - Enable USB2 ports
Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
port1, and so on. 0x01(Default).
**/
- uint8_t PortUsb20Enable[8];
+ UINT8 PortUsb20Enable[8];
/** Offset 0x025A - USB20 Over Current Pin
Over Current Pin number of USB 2.0 Port. 0x00(Default).
**/
- uint8_t PortUs20bOverCurrentPin[8];
+ UINT8 PortUs20bOverCurrentPin[8];
/** Offset 0x0262 - Enable USB3 ports
Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
port1, and so on. 0x01(Default).
**/
- uint8_t PortUsb30Enable[6];
+ UINT8 PortUsb30Enable[6];
/** Offset 0x0268 - USB20 Over Current Pin
Over Current Pin number of USB 3.0 Port. 0x01(Default).
**/
- uint8_t PortUs30bOverCurrentPin[6];
+ UINT8 PortUs30bOverCurrentPin[6];
/** Offset 0x026E - XDCI Support
Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode.
0:Disable, 1:PCI_Mode, 2:ACPI_mode
**/
- uint8_t UsbOtg;
+ UINT8 UsbOtg;
/** Offset 0x026F - Enable XHCI HSIC Support
Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t HsicSupportEnable;
+ UINT8 HsicSupportEnable;
/** Offset 0x0270 - Enable XHCI SSIC Support
Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for
port1. 0x00(Default).
**/
- uint8_t SsicPortEnable[2];
+ UINT8 SsicPortEnable[2];
/** Offset 0x0272 - SSIC Dlane PowerGating
Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint16_t DlanePwrGating;
+ UINT16 DlanePwrGating;
/** Offset 0x0274 - VT-d
Enable/Disable VT-d. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t VtdEnable;
+ UINT8 VtdEnable;
/** Offset 0x0275 - HDAudio Delay Timer
The delay timer after Azalia reset. 0x012C(Default).
**/
- uint16_t ResetWaitTimer;
+ UINT16 ResetWaitTimer;
/** Offset 0x0277 - SMI Lock bit
Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable,
1:Enable(Default).
$EN_DIS
**/
- uint8_t LockDownGlobalSmi;
+ UINT8 LockDownGlobalSmi;
/** Offset 0x0278 - RTC Lock Bits
Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t RtcLock;
+ UINT8 RtcLock;
/** Offset 0x0279 - XHCI SSIC RATE
Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series.
**/
- uint8_t SsicRate[2];
+ UINT8 SsicRate[2];
/** Offset 0x027B - SATA Test Mode Selection
Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint8_t SataTestMode;
+ UINT8 SataTestMode;
/** Offset 0x027C - SMBus Dynamic Power Gating
Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- uint16_t DynamicPowerGating;
+ UINT16 DynamicPowerGating;
/** Offset 0x027E - Max Snoop Latency
Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default).
**/
- uint16_t PcieRpLtrMaxSnoopLatency[6];
+ UINT16 PcieRpLtrMaxSnoopLatency[6];
/** Offset 0x028A - Snoop Latency Override
Snoop Latency Override for PCH PCIE. \n
@@ -1285,23 +1287,23 @@ struct FSP_S_CONFIG {
Manual:Manually enter override values.\n
Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).
**/
- uint8_t PcieRpSnoopLatencyOverrideMode[6];
+ UINT8 PcieRpSnoopLatencyOverrideMode[6];
/** Offset 0x0290 - Snoop Latency Value
LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).
**/
- uint16_t PcieRpSnoopLatencyOverrideValue[6];
+ UINT16 PcieRpSnoopLatencyOverrideValue[6];
/** Offset 0x029C - Snoop Latency Multiplier
LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns,
4:1048576ns, 5:33554432ns.
**/
- uint8_t PcieRpSnoopLatencyOverrideMultiplier[6];
+ UINT8 PcieRpSnoopLatencyOverrideMultiplier[6];
/** Offset 0x02A2 - Max Non-Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default).
**/
- uint16_t PcieRpLtrMaxNonSnoopLatency[6];
+ UINT16 PcieRpLtrMaxNonSnoopLatency[6];
/** Offset 0x02AE - Non Snoop Latency Override
Non Snoop Latency Override for PCH PCIE. \n
@@ -1309,229 +1311,231 @@ struct FSP_S_CONFIG {
Manual:Manually enter override values.\n
Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).
**/
- uint8_t PcieRpNonSnoopLatencyOverrideMode[6];
+ UINT8 PcieRpNonSnoopLatencyOverrideMode[6];
/** Offset 0x02B4 - Non Snoop Latency Value
LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).
**/
- uint16_t PcieRpNonSnoopLatencyOverrideValue[6];
+ UINT16 PcieRpNonSnoopLatencyOverrideValue[6];
/** Offset 0x02C0 - Non Snoop Latency Multiplier
LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default),
3:32768ns, 4:1048576ns, 5:33554432ns.
**/
- uint8_t PcieRpNonSnoopLatencyOverrideMultiplier[6];
+ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6];
/** Offset 0x02C6 - PCIE Root Port Slot Power Limit Scale
Specifies scale used for slot power limit value. 0x00(Default).
**/
- uint8_t PcieRpSlotPowerLimitScale[6];
+ UINT8 PcieRpSlotPowerLimitScale[6];
/** Offset 0x02CC - PCIE Root Port Slot Power Limit Value
Specifies upper limit on power supplie by slot. 0x00(Default).
**/
- uint8_t PcieRpSlotPowerLimitValue[6];
+ UINT8 PcieRpSlotPowerLimitValue[6];
/** Offset 0x02D2 - Skip Multi-Processor Initialization
When this is skipped, boot loader must initialize processors before SilicionInit
API. 0: Initialize(Default), <b>1: Skip
$EN_DIS
**/
- uint8_t SkipMpInit;
+ UINT8 SkipMpInit;
/** Offset 0x02D3 - DCI Auto Detect
Enable/disable DCI AUTO mode. Enabled(Default).
$EN_DIS
**/
- uint8_t DciAutoDetect;
+ UINT8 DciAutoDetect;
/** Offset 0x02D4 - Halt and Lock TCO Timer
Halt and Lock the TCO Timer (Watchdog).
0:No, 1:Yes (default)
**/
- uint8_t TcoTimerHaltLock;
+ UINT8 TcoTimerHaltLock;
/** Offset 0x02D5 - Power Button Override Period
specifies how long will PMC wait before initiating a global reset. 000b-4s(default),
001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.)
0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s
**/
- uint8_t PwrBtnOverridePeriod;
+ UINT8 PwrBtnOverridePeriod;
/** Offset 0x02D6 - Power Button Native Mode Disable
Disable power button native mode, when 1, this will result in the PMC logic constantly
seeing the power button as de-asserted. 0 (default))
$EN_DIS
**/
- uint8_t DisableNativePowerButton;
+ UINT8 DisableNativePowerButton;
/** Offset 0x02D7 - Power Button Debounce Mode
Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default)
$EN_DIS
**/
- uint8_t PowerButterDebounceMode;
+ UINT8 PowerButterDebounceMode;
/** Offset 0x02D8 - SDIO_TX_CMD_DLL_CNTL
SDIO_TX_CMD_DLL_CNTL. 0x505(Default).
**/
- uint32_t SdioTxCmdCntl;
+ UINT32 SdioTxCmdCntl;
/** Offset 0x02DC - SDIO_TX_DATA_DLL_CNTL1
SDIO_TX_DATA_DLL_CNTL1. 0xE(Default).
**/
- uint32_t SdioTxDataCntl1;
+ UINT32 SdioTxDataCntl1;
/** Offset 0x02E0 - SDIO_TX_DATA_DLL_CNTL2
SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default).
**/
- uint32_t SdioTxDataCntl2;
+ UINT32 SdioTxDataCntl2;
/** Offset 0x02E4 - SDIO_RX_CMD_DATA_DLL_CNTL1
SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default).
**/
- uint32_t SdioRxCmdDataCntl1;
+ UINT32 SdioRxCmdDataCntl1;
/** Offset 0x02E8 - SDIO_RX_CMD_DATA_DLL_CNTL2
SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).
**/
- uint32_t SdioRxCmdDataCntl2;
+ UINT32 SdioRxCmdDataCntl2;
/** Offset 0x02EC - SDCARD_TX_CMD_DLL_CNTL
SDCARD_TX_CMD_DLL_CNTL. 0x505(Default).
**/
- uint32_t SdcardTxCmdCntl;
+ UINT32 SdcardTxCmdCntl;
/** Offset 0x02F0 - SDCARD_TX_DATA_DLL_CNTL1
SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default).
**/
- uint32_t SdcardTxDataCntl1;
+ UINT32 SdcardTxDataCntl1;
/** Offset 0x02F4 - SDCARD_TX_DATA_DLL_CNTL2
SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default).
**/
- uint32_t SdcardTxDataCntl2;
+ UINT32 SdcardTxDataCntl2;
/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL1
SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default).
**/
- uint32_t SdcardRxCmdDataCntl1;
+ UINT32 SdcardRxCmdDataCntl1;
/** Offset 0x02FC - SDCARD_RX_STROBE_DLL_CNTL
SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default).
**/
- uint32_t SdcardRxStrobeCntl;
+ UINT32 SdcardRxStrobeCntl;
/** Offset 0x0300 - SDCARD_RX_CMD_DATA_DLL_CNTL2
SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).
**/
- uint32_t SdcardRxCmdDataCntl2;
+ UINT32 SdcardRxCmdDataCntl2;
/** Offset 0x0304 - EMMC_TX_CMD_DLL_CNTL
EMMC_TX_CMD_DLL_CNTL. 0x505(Default).
**/
- uint32_t EmmcTxCmdCntl;
+ UINT32 EmmcTxCmdCntl;
/** Offset 0x0308 - EMMC_TX_DATA_DLL_CNTL1
EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default).
**/
- uint32_t EmmcTxDataCntl1;
+ UINT32 EmmcTxDataCntl1;
/** Offset 0x030C - EMMC_TX_DATA_DLL_CNTL2
EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default).
**/
- uint32_t EmmcTxDataCntl2;
+ UINT32 EmmcTxDataCntl2;
/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL1
EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default).
**/
- uint32_t EmmcRxCmdDataCntl1;
+ UINT32 EmmcRxCmdDataCntl1;
/** Offset 0x0314 - EMMC_RX_STROBE_DLL_CNTL
EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default).
**/
- uint32_t EmmcRxStrobeCntl;
+ UINT32 EmmcRxStrobeCntl;
/** Offset 0x0318 - EMMC_RX_CMD_DATA_DLL_CNTL2
EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default).
**/
- uint32_t EmmcRxCmdDataCntl2;
+ UINT32 EmmcRxCmdDataCntl2;
/** Offset 0x031C - EMMC_MASTER_DLL_CNTL
EMMC_MASTER_DLL_CNTL. 0x001(Default).
**/
- uint32_t EmmcMasterSwCntl;
+ UINT32 EmmcMasterSwCntl;
/** Offset 0x0320 - PCIe Selectable De-emphasis
When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis
for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default).
**/
- uint8_t PcieRpSelectableDeemphasis[6];
+ UINT8 PcieRpSelectableDeemphasis[6];
/** Offset 0x0326
**/
- uint8_t UnusedUpdSpace4;
+ UINT8 UnusedUpdSpace4;
/** Offset 0x0327 - Monitor Mwait Enable
Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux
based OS, this should be Disabled. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- uint8_t MonitorMwaitEnable;
+ UINT8 MonitorMwaitEnable;
/** Offset 0x0328
**/
- uint8_t ReservedFspsUpd[8];
-} __attribute__((packed));
+ UINT8 ReservedFspsUpd[8];
+} FSP_S_CONFIG;
/** Fsp S Test Configuration
**/
-struct FSP_S_TEST_CONFIG {
+typedef struct {
/** Offset 0x0330
**/
- uint32_t Signature;
+ UINT32 Signature;
/** Offset 0x0334
**/
- uint8_t ReservedFspsTestUpd[12];
-} __attribute__((packed));
+ UINT8 ReservedFspsTestUpd[12];
+} FSP_S_TEST_CONFIG;
/** Fsp S Restricted Configuration
**/
-struct FSP_S_RESTRICTED_CONFIG {
+typedef struct {
/** Offset 0x0340
**/
- uint32_t Signature;
+ UINT32 Signature;
/** Offset 0x0344
**/
- uint8_t ReservedFspsRestrictedUpd[12];
-} __attribute__((packed));
+ UINT8 ReservedFspsRestrictedUpd[12];
+} FSP_S_RESTRICTED_CONFIG;
/** Fsp S UPD Configuration
**/
-struct FSPS_UPD {
+typedef struct {
/** Offset 0x0000
**/
- struct FSP_UPD_HEADER FspUpdHeader;
+ FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
- struct FSP_S_CONFIG FspsConfig;
+ FSP_S_CONFIG FspsConfig;
/** Offset 0x0330
**/
- struct FSP_S_TEST_CONFIG FspsTestConfig;
+ FSP_S_TEST_CONFIG FspsTestConfig;
/** Offset 0x0340
**/
- struct FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;
+ FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;
/** Offset 0x0350
**/
- uint16_t UpdTerminator;
-} __attribute__((packed));
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack(pop)
#endif
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index 06d2b58193..45b20a0989 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -18,6 +18,7 @@
#include <stddef.h>
#include <stdint.h>
+#include <fsp/soc_binding.h>
/*
* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
@@ -77,13 +78,11 @@ struct lpddr4_swizzle_cfg {
struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
};
-struct FSP_M_CONFIG;
-
/*
* Initialize default LPDDR4 settings with provided speed. No logical channels
* are enabled. Subsequent calls to logical channel enabling are required.
*/
-void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed);
+void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed);
/*
* Enable logical channel providing the full lpddr4_swizzle_config to
@@ -91,7 +90,7 @@ void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed);
* memory width per logical channel -- i.e. 2 physical channels are configured
* to the memory reference code.
*/
-void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan,
+void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan,
int rank_density, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg);
@@ -115,7 +114,7 @@ struct lpddr4_cfg {
* Initialize LPDDR4 settings by the provided lpddr4_cfg information and sku id.
* The sku id is an index into the sku array within the lpddr4_cfg struct.
*/
-void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg,
+void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
const struct lpddr4_cfg *lpcfg, size_t sku_id);
void save_lpddr4_dimm_info(const struct lpddr4_cfg *lpcfg, size_t mem_sku);
diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h
index 5b76f65856..6ae46b69dd 100644
--- a/src/soc/intel/apollolake/include/soc/romstage.h
+++ b/src/soc/intel/apollolake/include/soc/romstage.h
@@ -21,7 +21,7 @@
#include <arch/cpu.h>
#include <fsp/api.h>
-void mainboard_memory_init_params(struct FSPM_UPD *mupd);
+void mainboard_memory_init_params(FSPM_UPD *mupd);
void mainboard_save_dimm_info(void);
#endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 9aac1f0f97..0f553ee97f 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -19,10 +19,10 @@
#include <smbios.h>
#include <soc/meminit.h>
#include <stddef.h> /* required for FspmUpd.h */
-#include <soc/fsp/FspmUpd.h>
+#include <fsp/soc_binding.h>
#include <string.h>
-static void set_lpddr4_defaults(struct FSP_M_CONFIG *cfg)
+static void set_lpddr4_defaults(FSP_M_CONFIG *cfg)
{
/* Enable memory down BGA since it's the only LPDDR4 packaging. */
cfg->Package = 1;
@@ -80,7 +80,7 @@ static void set_lpddr4_defaults(struct FSP_M_CONFIG *cfg)
cfg->Ch3_OdtConfig = 0;
}
-void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed)
+void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed)
{
uint8_t profile;
@@ -107,7 +107,7 @@ void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed)
set_lpddr4_defaults(cfg);
}
-static void enable_logical_chan0(struct FSP_M_CONFIG *cfg,
+static void enable_logical_chan0(FSP_M_CONFIG *cfg,
int rank_density, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg)
{
@@ -152,7 +152,7 @@ static void enable_logical_chan0(struct FSP_M_CONFIG *cfg,
memcpy(&cfg->Ch1_Bit_swizzling[24], &chan->dqs[LP4_DQS3], sz);
}
-static void enable_logical_chan1(struct FSP_M_CONFIG *cfg,
+static void enable_logical_chan1(FSP_M_CONFIG *cfg,
int rank_density, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg)
{
@@ -197,7 +197,7 @@ static void enable_logical_chan1(struct FSP_M_CONFIG *cfg,
memcpy(&cfg->Ch3_Bit_swizzling[24], &chan->dqs[LP4_DQS3], sz);
}
-void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan,
+void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan,
int rank_density, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg)
{
@@ -220,7 +220,7 @@ void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan,
}
}
-void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg,
+void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
const struct lpddr4_cfg *lpcfg, size_t sku_id)
{
const struct lpddr4_sku *sku;
@@ -262,11 +262,11 @@ void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku)
{
int channel, dimm, dimm_max, index;
size_t hob_size;
- const struct DIMM_INFO *src_dimm;
+ const DIMM_INFO *src_dimm;
struct dimm_info *dest_dimm;
struct memory_info *mem_info;
- const struct CHANNEL_INFO *channel_info;
- const struct FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
+ const CHANNEL_INFO *channel_info;
+ const FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
if (mem_sku >= lp4cfg->num_skus) {
printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n",
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index 4bfdee4b75..3e62d818fa 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -59,7 +59,7 @@ void reset_prepare(void)
printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw));
}
-void chipset_handle_reset(enum fsp_status status)
+void chipset_handle_reset(uint32_t status)
{
switch(status) {
case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 6b58aa5305..ebd6287e4a 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -133,7 +133,7 @@ asmlinkage void car_stage_entry(void)
run_postcar_phase(&pcf);
}
-static void fill_console_params(struct FSPM_UPD *mupd)
+static void fill_console_params(FSPM_UPD *mupd)
{
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE;
@@ -148,7 +148,7 @@ static void fill_console_params(struct FSPM_UPD *mupd)
}
}
-void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
{
fill_console_params(mupd);
mainboard_memory_init_params(mupd);
@@ -167,7 +167,7 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
}
__attribute__ ((weak))
-void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+void mainboard_memory_init_params(FSPM_UPD *mupd)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 11:23:38 +0000