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-rw-r--r--src/soc/mediatek/common/pcie.c2
-rw-r--r--src/soc/qualcomm/common/pcie_common.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c
index febb76dc77..fd93665f8a 100644
--- a/src/soc/mediatek/common/pcie.c
+++ b/src/soc/mediatek/common/pcie.c
@@ -211,7 +211,7 @@ void mtk_pcie_domain_set_resources(struct device *dev)
pci_domain_set_resources(dev);
}
-enum cb_err lb_fill_pcie(struct lb_pcie *pcie)
+enum cb_err fill_lb_pcie(struct lb_pcie *pcie)
{
if (!pci_root_bus())
return CB_ERR;
diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c
index e27b0fcbfb..2f53e28028 100644
--- a/src/soc/qualcomm/common/pcie_common.c
+++ b/src/soc/qualcomm/common/pcie_common.c
@@ -414,7 +414,7 @@ static enum cb_err qcom_dw_pcie_enable(struct qcom_pcie_cntlr_t *pcie)
* Fill coreboot table with PCIe info.
* It allows exporting this info to payloads.
*/
-enum cb_err lb_fill_pcie(struct lb_pcie *pcie)
+enum cb_err fill_lb_pcie(struct lb_pcie *pcie)
{
pcie_cntlr_cfg_t *pcierc = qcom_pcie_cfg.cntlr_cfg;
pcie->ctrl_base = (uintptr_t)pcierc->dbi_base;