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-rw-r--r--src/soc/intel/alderlake/chipset.cb1
-rw-r--r--src/soc/intel/alderlake/include/soc/pci_devs.h2
2 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index cd9ebf9192..19411a6d20 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -60,7 +60,6 @@ chip soc/intel/alderlake
device pci 0e.0 alias vmd off end
device pci 10.0 alias thc0 off end
device pci 10.1 alias thc1 off end
- device pci 10.2 alias cnvi_bt off end
device pci 12.0 alias ish off end
device pci 12.6 alias gspi2 off end
device pci 13.0 alias gspi3 off end
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index 6a114ae61c..23cf24810d 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -73,10 +73,8 @@
#define PCH_DEV_SLOT_SIO0 0x10
#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 0)
#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 1)
-#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2)
#define PCH_DEV_THC0 _PCH_DEV(SIO0, 0)
#define PCH_DEV_THC1 _PCH_DEV(SIO0, 1)
-#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2)
#define PCH_DEV_SLOT_ISH 0x12
#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0)