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-rw-r--r--src/soc/mediatek/mt8195/include/soc/addressmap.h1
-rw-r--r--src/soc/mediatek/mt8195/pll.c14
2 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h
index f2714dab3a..a5c4b0d2a2 100644
--- a/src/soc/mediatek/mt8195/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h
@@ -49,6 +49,7 @@ enum {
SSPM_SRAM_BASE = IO_PHYS + 0x00400000,
SSPM_CFG_BASE = IO_PHYS + 0x00440000,
SCP_CFG_BASE = IO_PHYS + 0x00700000,
+ SCP_ADSP_CFG_BASE = IO_PHYS + 0x00720000,
DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000,
DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000,
DPM_CFG_BASE = IO_PHYS + 0x00940000,
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c
index df4ae3039d..046008cbd6 100644
--- a/src/soc/mediatek/mt8195/pll.c
+++ b/src/soc/mediatek/mt8195/pll.c
@@ -28,6 +28,14 @@ struct mt8195_pericfg_ao_regs {
check_member(mt8195_pericfg_ao_regs, peri_module_sw_cg_0_set, 0x0010);
static struct mt8195_pericfg_ao_regs *const mt8195_pericfg_ao = (void *)PERICFG_AO_BASE;
+struct mt8195_scp_adsp_regs {
+ u32 reserved1[96];
+ u32 audiodsp_ck_cg; /* 0x180 */
+};
+check_member(mt8195_scp_adsp_regs, audiodsp_ck_cg, 0x0180);
+static struct mt8195_scp_adsp_regs *const mt8195_scp_adsp =
+ (void *)SCP_ADSP_CFG_BASE;
+
enum mux_id {
TOP_AXI_SEL,
TOP_SPM_SEL,
@@ -760,6 +768,12 @@ void mt_pll_init(void)
/* turn off unused clock */
write32(&mt8195_pericfg_ao->peri_module_sw_cg_0_set, 0x10);
+
+ /* scp_dsp for audio */
+ clrbits32(&mt8195_scp_adsp->audiodsp_ck_cg, BIT(0));
+
+ /* audio 26M */
+ setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(4));
}
void mt_pll_raise_little_cpu_freq(u32 freq)