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-rw-r--r--src/soc/intel/alderlake/fsp_params.c2
-rw-r--r--src/soc/intel/meteorlake/fsp_params.c2
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index b43203038f..46555b0719 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1342,7 +1342,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
* 1 | After TCSS initialization completed | for TCSS specific init
* 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init
*/
-void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
+void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
{
switch (phase_index) {
case 1:
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 971fa3360d..a02d4b99c6 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -838,7 +838,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
* 1 | After TCSS initialization completed | for TCSS specific init
* 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init
*/
-void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
+void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
{
switch (phase_index) {
case 1:
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 358536ea43..33269356c8 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -659,7 +659,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
* ------- + ------------------------------------------------ + -------------------------------
* 1 | After TCSS initialization completed | for TCSS specific init
*/
-void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
+void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
{
switch (phase_index) {
case 1: