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-rw-r--r--src/soc/intel/alderlake/Kconfig2
-rw-r--r--src/soc/intel/alderlake/acpi/southbridge.asl3
-rw-r--r--src/soc/intel/alderlake/pmc.c14
3 files changed, 16 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index cdf127f36d..c75753ba23 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -48,6 +48,8 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
+ select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
+ select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl
index 59bcf7461f..8300c23b7f 100644
--- a/src/soc/intel/alderlake/acpi/southbridge.asl
+++ b/src/soc/intel/alderlake/acpi/southbridge.asl
@@ -38,8 +38,5 @@
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
-/* Intel Power Engine Plug-in */
-#include <soc/intel/common/block/acpi/acpi/pep.asl>
-
/* GbE 0:1f.6 */
#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c
index dd88b1d461..0e0a568a88 100644
--- a/src/soc/intel/alderlake/pmc.c
+++ b/src/soc/intel/alderlake/pmc.c
@@ -11,10 +11,12 @@
#include <device/mmio.h>
#include <device/device.h>
#include <drivers/intel/pmc_mux/chip.h>
+#include <intelblocks/acpi.h>
#include <intelblocks/pmc.h>
#include <intelblocks/pmc_ipc.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
+#include <soc/cpu.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/soc_chip.h>
@@ -122,6 +124,18 @@ static void soc_pmc_fill_ssdt(const struct device *dev)
acpigen_pop_len(); /* PMC Device */
acpigen_pop_len(); /* Scope */
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) {
+ const struct soc_pmc_lpm adl_pmc_lpm = {
+ .num_substates = 8,
+ .num_req_regs = 6,
+ .lpm_ipc_offset = 0x1000,
+ .req_reg_stride = 0x30,
+ .lpm_enable_mask = get_supported_lpm_mask(),
+ };
+
+ generate_acpi_power_engine_with_lpm(&adl_pmc_lpm);
+ }
+
printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name,
dev_path(dev));
}