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-rw-r--r--src/soc/intel/xeon_sp/skx/acpi.c73
-rw-r--r--src/soc/intel/xeon_sp/skx/soc_acpi.c42
2 files changed, 64 insertions, 51 deletions
diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c
index f0b7df9c38..c14e7c8aea 100644
--- a/src/soc/intel/xeon_sp/skx/acpi.c
+++ b/src/soc/intel/xeon_sp/skx/acpi.c
@@ -137,82 +137,53 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->sci_int = acpi_sci_irq();
- /* TODO: enabled SMM mode switch when SMM handlers are set up. */
- if (0 && permanent_smi_handler()) {
+ if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
}
- /* Power Control */
fadt->pm1a_evt_blk = pmbase + PM1_STS;
fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
- fadt->pm2_cnt_blk = pmbase + PM2_CNT;
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
+
fadt->gpe0_blk = pmbase + GPE0_STS(0);
- /* Control Registers - Length */
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
+
+ /* GPE0 STS/EN pairs each 32 bits wide. */
fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
- fadt->duty_offset = 1;
- fadt->duty_width = 0;
- /* RTC Registers */
- fadt->day_alrm = 0x0d;
- fadt->mon_alrm = 0x00;
- fadt->century = 0x00;
- fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+ fadt->duty_offset = 1;
+ fadt->day_alrm = 0xd;
fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
- ACPI_FADT_SLEEP_TYPE | ACPI_FADT_S4_RTC_WAKE |
- ACPI_FADT_PLATFORM_CLOCK;
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_PLATFORM_CLOCK;
- /* PM1 Status & PM1 Enable */
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
- fadt->x_pm1a_evt_blk.addrh = 0x00;
- /* PM1 Control Registers */
fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
- fadt->x_pm1a_cnt_blk.addrh = 0x00;
-
- /* PM2 Control Registers */
- fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
- fadt->x_pm2_cnt_blk.addrh = 0x00;
-
- /* PM1 Timer Register */
- fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
- fadt->x_pm_tmr_blk.addrh = 0x00;
-
- /* General-Purpose Event Registers */
+
+ /*
+ * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
+ * The bit_width field intentionally overflows here.
+ * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
+ * seems to work fine on Linux 5.0 and Windows 10.
+ */
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */
+ fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0x00;
+ fadt->x_gpe0_blk.addrh = 0;
}
unsigned long southbridge_write_acpi_tables(const struct device *device,
diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c
index 56ed0ce17b..7462d72b7a 100644
--- a/src/soc/intel/xeon_sp/skx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c
@@ -55,6 +55,48 @@ uint32_t soc_read_sci_irq_select(void)
return pci_read_config32(dev, PMC_ACPI_CNT);
}
+void soc_fill_fadt(acpi_fadt_t *fadt)
+{
+ const uint16_t pmbase = ACPI_BASE_ADDRESS;
+
+ /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */
+ fadt->flags &= ~(ACPI_FADT_SEALED_CASE);
+ fadt->flags |= ACPI_FADT_SLEEP_TYPE;
+
+ fadt->pm2_cnt_blk = pmbase + PM2_CNT;
+ fadt->pm_tmr_blk = pmbase + PM1_TMR;
+
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+
+ fadt->duty_width = 0;
+
+ /* RTC Registers */
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ /* PM2 Control Registers */
+ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+ fadt->x_pm2_cnt_blk.addrh = 0x00;
+
+ /* PM1 Timer Register */
+ fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+ fadt->x_pm_tmr_blk.addrh = 0x00;
+
+}
+
void uncore_inject_dsdt(const struct device *device)
{
size_t hob_size;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 15:11:30 +0000