diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/bootblock.c | 80 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/early_cache.c | 81 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/cpu.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/bootblock.c | 77 |
5 files changed, 85 insertions, 155 deletions
diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c index c3cb138473..c42ac0ac7c 100644 --- a/src/soc/amd/cezanne/bootblock.c +++ b/src/soc/amd/cezanne/bootblock.c @@ -4,92 +4,14 @@ #include <amdblocks/cpu.h> #include <bootblock_common.h> #include <console/console.h> -#include <cpu/amd/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/tsc.h> -#include <soc/iomap.h> #include <soc/southbridge.h> #include <soc/psp_transfer.h> #include <stdint.h> -/* - * PSP performs the memory training and setting up DRAM map prior to x86 cores being released. - * Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, route lower memory addresses - * covered by fixed MTRRs to DRAM except for 0xa0000-0xc0000. - */ -static void set_caching(void) -{ - msr_t top_mem; - msr_t sys_cfg; - msr_t mtrr_def_type; - msr_t fixed_mtrr_ram; - msr_t fixed_mtrr_mmio; - struct var_mtrr_context mtrr_ctx; - - var_mtrr_context_init(&mtrr_ctx, NULL); - top_mem = rdmsr(TOP_MEM); - /* Enable RdDram and WrDram attributes in fixed MTRRs. */ - sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; - - /* Fixed MTRR constants. */ - fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); - fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = - ((MTRR_TYPE_UNCACHEABLE) << 0) | - ((MTRR_TYPE_UNCACHEABLE) << 8) | - ((MTRR_TYPE_UNCACHEABLE) << 16) | - ((MTRR_TYPE_UNCACHEABLE) << 24); - - /* Prep default MTRR type. */ - mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); - mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; - mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; - mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; - - disable_cache(); - - wrmsr(SYSCFG_MSR, sys_cfg); - - clear_all_var_mtrr(); - - var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); - /* TODO: check if we should always mark 16 MByte below 4 GByte as WRPROT */ - var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ - wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); - wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); - - wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); - - /* Enable Fixed and Variable MTRRs. */ - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; - sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; - /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once - MP init happens in coreboot proper it can be knocked down. */ - wrmsr(SYSCFG_MSR, sys_cfg); - - enable_cache(); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - set_caching(); + early_cache_setup(); write_resume_eip(); enable_pci_mmconf(); diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc index 808679dfea..532bb32918 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y) +bootblock-y += early_cache.c bootblock-y += pre_c.S bootblock-y += write_resume_eip.c romstage-y += memmap.c diff --git a/src/soc/amd/common/block/cpu/noncar/early_cache.c b/src/soc/amd/common/block/cpu/noncar/early_cache.c new file mode 100644 index 0000000000..b9650a96a7 --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/early_cache.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/cpu.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <soc/iomap.h> + +/* + * PSP performs the memory training and setting up DRAM map prior to x86 cores being released. + * Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, route lower memory addresses + * covered by fixed MTRRs to DRAM except for 0xa0000-0xc0000. + */ +void early_cache_setup(void) +{ + msr_t top_mem; + msr_t sys_cfg; + msr_t mtrr_def_type; + msr_t fixed_mtrr_ram; + msr_t fixed_mtrr_mmio; + struct var_mtrr_context mtrr_ctx; + + var_mtrr_context_init(&mtrr_ctx, NULL); + top_mem = rdmsr(TOP_MEM); + /* Enable RdDram and WrDram attributes in fixed MTRRs. */ + sys_cfg = rdmsr(SYSCFG_MSR); + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; + + /* Fixed MTRR constants. */ + fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); + fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = + ((MTRR_TYPE_UNCACHEABLE) << 0) | + ((MTRR_TYPE_UNCACHEABLE) << 8) | + ((MTRR_TYPE_UNCACHEABLE) << 16) | + ((MTRR_TYPE_UNCACHEABLE) << 24); + + /* Prep default MTRR type. */ + mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); + mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; + mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; + mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; + + disable_cache(); + + wrmsr(SYSCFG_MSR, sys_cfg); + + clear_all_var_mtrr(); + + var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); + /* TODO: check if we should always mark 16 MByte below 4 GByte as WRPROT */ + var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ + wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); + wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); + + wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); + + /* Enable Fixed and Variable MTRRs. */ + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; + sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; + /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once + MP init happens in coreboot proper it can be knocked down. */ + wrmsr(SYSCFG_MSR, sys_cfg); + + enable_cache(); +} diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 0627bc1377..6576c3b993 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -3,6 +3,7 @@ #ifndef AMD_BLOCK_CPU_H #define AMD_BLOCK_CPU_H +void early_cache_setup(void); int get_cpu_count(void); void set_cstate_io_addr(void); void write_resume_eip(void); diff --git a/src/soc/amd/picasso/bootblock.c b/src/soc/amd/picasso/bootblock.c index 7d1f01cec8..88c03af0a9 100644 --- a/src/soc/amd/picasso/bootblock.c +++ b/src/soc/amd/picasso/bootblock.c @@ -6,10 +6,6 @@ #include <amdblocks/reset.h> #include <bootblock_common.h> #include <console/console.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> #include <cpu/x86/tsc.h> #include <pc80/mc146818rtc.h> #include <soc/psp_transfer.h> @@ -17,80 +13,9 @@ #include <soc/i2c.h> #include <amdblocks/amd_pci_mmconf.h> -/* PSP performs the memory training and setting up DRAM map prior to x86 cores - being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, - route lower memory addresses covered by fixed MTRRs to DRAM except for - 0xa0000-0xc0000 . */ -static void set_caching(void) -{ - msr_t top_mem; - msr_t sys_cfg; - msr_t mtrr_def_type; - msr_t fixed_mtrr_ram; - msr_t fixed_mtrr_mmio; - struct var_mtrr_context mtrr_ctx; - - var_mtrr_context_init(&mtrr_ctx, NULL); - top_mem = rdmsr(TOP_MEM); - /* Enable RdDram and WrDram attributes in fixed MTRRs. */ - sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; - - /* Fixed MTRR constants. */ - fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); - fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = - ((MTRR_TYPE_UNCACHEABLE) << 0) | - ((MTRR_TYPE_UNCACHEABLE) << 8) | - ((MTRR_TYPE_UNCACHEABLE) << 16) | - ((MTRR_TYPE_UNCACHEABLE) << 24); - - /* Prep default MTRR type. */ - mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); - mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; - mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; - mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; - - disable_cache(); - - wrmsr(SYSCFG_MSR, sys_cfg); - - clear_all_var_mtrr(); - - var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); - var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ - wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); - wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); - - wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); - - /* Enable Fixed and Variable MTRRs. */ - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; - sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; - /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once - MP init happens in coreboot proper it can be knocked down. */ - wrmsr(SYSCFG_MSR, sys_cfg); - - enable_cache(); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - set_caching(); + early_cache_setup(); write_resume_eip(); enable_pci_mmconf(); |