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-rw-r--r--src/soc/intel/alderlake/chip.h81
-rw-r--r--src/soc/intel/alderlake/fsp_params.c58
-rw-r--r--src/soc/intel/alderlake/romstage/fsp_params.c20
3 files changed, 78 insertions, 81 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index e77a3dc114..e7e2f20805 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -195,9 +195,9 @@ struct soc_intel_alderlake_config {
/* Enable S0iX support */
int s0ix_enable;
/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
- uint8_t TcssD3HotDisable;
+ uint8_t tcss_d3_hot_disable;
/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
- uint8_t TcssD3ColdDisable;
+ uint8_t tcss_d3_cold_disable;
/* Enable DPTF support */
int dptf_enable;
@@ -227,7 +227,7 @@ struct soc_intel_alderlake_config {
SaGv_FixedPoint2,
SaGv_FixedPoint3,
SaGv_Enabled,
- } SaGv;
+ } sagv;
/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;
@@ -243,31 +243,31 @@ struct soc_intel_alderlake_config {
struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
/* SATA related */
- uint8_t SataEnable;
- uint8_t SataMode;
- uint8_t SataSalpSupport;
- uint8_t SataPortsEnable[8];
- uint8_t SataPortsDevSlp[8];
+ uint8_t sata_mode;
+ uint8_t sata_salp_support;
+ uint8_t sata_ports_enable[8];
+ uint8_t sata_ports_dev_slp[8];
/*
* Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the SATA Power Optimizer.
*/
- uint8_t SataPwrOptimizeDisable;
+ uint8_t sata_pwr_optimize_disable;
/*
* SATA Port Enable Dito Config.
* Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
*/
- uint8_t SataPortsEnableDitoConfig[8];
+ uint8_t sata_ports_enable_dito_config[8];
/* SataPortsDmVal is the DITO multiplier. Default is 15. */
- uint8_t SataPortsDmVal[8];
+ uint8_t sata_ports_dm_val[8];
+
/* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
- uint16_t SataPortsDitoVal[8];
+ uint16_t sata_ports_dito_val[8];
/* Audio related */
- uint8_t PchHdaDspEnable;
+ uint8_t pch_hda_dsp_enable;
/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
enum {
@@ -275,15 +275,15 @@ struct soc_intel_alderlake_config {
HDA_TMODE_4T = 2,
HDA_TMODE_8T = 3,
HDA_TMODE_16T = 4,
- } PchHdaIDispLinkTmode;
+ } pch_hda_idisp_link_tmode;
/* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */
enum {
HDA_LINKFREQ_48MHZ = 3,
HDA_LINKFREQ_96MHZ = 4,
- } PchHdaIDispLinkFrequency;
+ } pch_hda_idisp_link_frequency;
- bool PchHdaIDispCodecEnable;
+ bool pch_hda_idisp_codec_enable;
struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS];
struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS];
@@ -311,8 +311,8 @@ struct soc_intel_alderlake_config {
IGD_SM_52MB = 0xFC,
IGD_SM_56MB = 0xFD,
IGD_SM_60MB = 0xFE,
- } IgdDvmt50PreAlloc;
- uint8_t SkipExtGfxScan;
+ } igd_dvmt50_pre_alloc;
+ uint8_t skip_ext_gfx_scan;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;
@@ -328,21 +328,21 @@ struct soc_intel_alderlake_config {
* PchSerialIoLegacyUart,
* PchSerialIoSkipInit
*/
- uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
- uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
- uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
+ uint8_t serial_io_i2c_mode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
+ uint8_t serial_io_gspi_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ uint8_t serial_io_uart_mode[CONFIG_SOC_INTEL_UART_DEV_MAX];
/*
* GSPIn Default Chip Select Mode:
* 0:Hardware Mode,
* 1:Software Mode
*/
- uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ uint8_t serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/*
* GSPIn Default Chip Select State:
* 0: Low,
* 1: High
*/
- uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ uint8_t serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/* Debug interface selection */
enum {
@@ -357,10 +357,10 @@ struct soc_intel_alderlake_config {
uint8_t pch_isclk;
/* CNVi BT Core Enable/Disable */
- bool CnviBtCore;
+ bool cnvi_bt_core;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
- bool CnviBtAudioOffload;
+ bool cnvi_bt_audio_offload;
/*
* These GPIOs will be programmed by the IOM to handle biasing of the
@@ -379,10 +379,7 @@ struct soc_intel_alderlake_config {
* Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
* on the motherboard.
*/
- uint16_t TcssAuxOri;
-
- /* Connect Topology Command timeout value */
- uint16_t ITbtConnectTopologyTimeoutInMs;
+ uint16_t tcss_aux_ori;
/*
* Override GPIO PM configuration:
@@ -408,8 +405,8 @@ struct soc_intel_alderlake_config {
* Port config
* 0:Disabled, 1:eDP, 2:MIPI DSI
*/
- uint8_t DdiPortAConfig;
- uint8_t DdiPortBConfig;
+ uint8_t ddi_portA_config;
+ uint8_t ddi_portB_config;
/* Enable(1)/Disable(0) HPD/DDC */
uint8_t ddi_ports_config[DDI_PORT_COUNT];
@@ -417,7 +414,7 @@ struct soc_intel_alderlake_config {
/* Hybrid storage mode enable (1) / disable (0)
* This mode makes FSP detect Optane and NVME and set PCIe lane mode
* accordingly */
- uint8_t HybridStorageMode;
+ uint8_t hybrid_storage_mode;
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
/* eMMC HS400 mode */
@@ -441,19 +438,19 @@ struct soc_intel_alderlake_config {
* Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the DMI Power Optimizer.
*/
- uint8_t DmiPwrOptimizeDisable;
+ uint8_t dmi_power_optimize_disable;
/*
* Enable(1)/Disable(0) CPU Replacement check.
* Default 0. Setting this to 1 to check CPU replacement.
*/
- uint8_t CpuReplacementCheck;
+ uint8_t cpu_replacement_check;
/* ISA Serial Base selection. */
enum {
ISA_SERIAL_BASE_ADDR_3F8,
ISA_SERIAL_BASE_ADDR_2F8,
- } IsaSerialUartBase;
+ } isa_serial_uart_base;
/* structure containing various settings for PCH FIVRs */
struct {
@@ -480,7 +477,7 @@ struct soc_intel_alderlake_config {
*/
struct vr_config domain_vr_config[NUM_VR_DOMAINS];
- uint16_t MaxDramSpeed;
+ uint16_t max_dram_speed;
enum {
SLP_S3_ASSERTION_DEFAULT,
@@ -532,7 +529,7 @@ struct soc_intel_alderlake_config {
} pch_reset_power_cycle_duration;
/* Platform Power Pmax */
- uint16_t PsysPmax;
+ uint16_t platform_pmax;
/*
* FivrRfiFrequency
* PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
@@ -541,7 +538,7 @@ struct soc_intel_alderlake_config {
* 0-1918*100 KHz (Up to 191.8MHz) for 24MHz clock
* 0-1535*100 KHz (Up to 153.5MHz) for 19MHz clock
*/
- uint32_t FivrRfiFrequency;
+ uint32_t fivr_rfi_frequency;
/*
* FivrSpreadSpectrum
* Set the Spread Spectrum Range.
@@ -549,16 +546,16 @@ struct soc_intel_alderlake_config {
* Each Range is translated to an encoded value for FIVR register.
* 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
*/
- uint8_t FivrSpreadSpectrum;
+ uint8_t fivr_spread_spectrum;
/* Enable or Disable Acoustic Noise Mitigation feature */
- uint8_t AcousticNoiseMitigation;
+ uint8_t acoustic_noise_mitigation;
/* Disable Fast Slew Rate for Deep Package C States for VR domains */
- uint8_t FastPkgCRampDisable[NUM_VR_DOMAINS];
+ uint8_t fast_pkg_c_ramp_disable[NUM_VR_DOMAINS];
/*
* Slew Rate configuration for Deep Package C States for VR domains
* 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values
*/
- uint8_t SlowSlewRate[NUM_VR_DOMAINS];
+ uint8_t slow_slew_rate[NUM_VR_DOMAINS];
/* Energy-Performance Preference (HWP feature) */
bool enable_energy_perf_pref;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index b4e833bf55..90ecf86d05 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -337,16 +337,16 @@ static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
- s_cfg->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
+ s_cfg->SerialIoI2cMode[i] = config->serial_io_i2c_mode[i];
for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
- s_cfg->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
- s_cfg->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
- s_cfg->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
+ s_cfg->SerialIoSpiMode[i] = config->serial_io_gspi_mode[i];
+ s_cfg->SerialIoSpiCsMode[i] = config->serial_io_gspi_cs_mode[i];
+ s_cfg->SerialIoSpiCsState[i] = config->serial_io_gspi_cs_state[i];
}
for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
- s_cfg->SerialIoUartMode[i] = config->SerialIoUartMode[i];
+ s_cfg->SerialIoUartMode[i] = config->serial_io_uart_mode[i];
}
static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
@@ -393,7 +393,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
DEV_PTR(tcss_usb3_port4),
};
- s_cfg->TcssAuxOri = config->TcssAuxOri;
+ s_cfg->TcssAuxOri = config->tcss_aux_ori;
/* Explicitly clear this field to avoid using defaults */
memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg));
@@ -406,8 +406,8 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
s_cfg->ITbtConnectTopologyTimeoutInMs = 0;
/* D3Hot and D3Cold for TCSS */
- s_cfg->D3HotEnable = !config->TcssD3HotDisable;
- s_cfg->D3ColdEnable = !config->TcssD3ColdDisable;
+ s_cfg->D3HotEnable = !config->tcss_d3_hot_disable;
+ s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable;
s_cfg->UsbTcPortEn = 0;
for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {
@@ -497,11 +497,11 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
/* SATA */
s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
if (s_cfg->SataEnable) {
- s_cfg->SataMode = config->SataMode;
- s_cfg->SataSalpSupport = config->SataSalpSupport;
- memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable,
+ s_cfg->SataMode = config->sata_mode;
+ s_cfg->SataSalpSupport = config->sata_salp_support;
+ memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable,
sizeof(s_cfg->SataPortsEnable));
- memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp,
+ memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp,
sizeof(s_cfg->SataPortsDevSlp));
}
@@ -511,17 +511,17 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
* Boards not needing the optimizers explicitly disables them by setting
* these disable variables to 1 in devicetree overrides.
*/
- s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
+ s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable);
/*
* Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
* SataPortsDmVal is the DITO multiplier. Default is 15.
* SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms.
* The default values can be changed from devicetree.
*/
- for (size_t i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) {
- if (config->SataPortsEnableDitoConfig[i]) {
- s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i];
- s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i];
+ for (size_t i = 0; i < ARRAY_SIZE(config->sata_ports_enable_dito_config); i++) {
+ if (config->sata_ports_enable_dito_config[i]) {
+ s_cfg->SataPortsDmVal[i] = config->sata_ports_dm_val[i];
+ s_cfg->SataPortsDitoVal[i] = config->sata_ports_dito_val[i];
}
}
}
@@ -548,8 +548,8 @@ static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
{
/* CNVi */
s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
- s_cfg->CnviBtCore = config->CnviBtCore;
- s_cfg->CnviBtAudioOffload = config->CnviBtAudioOffload;
+ s_cfg->CnviBtCore = config->cnvi_bt_core;
+ s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload;
/* Assert if CNVi BT is enabled without CNVi being enabled. */
assert(s_cfg->CnviMode || !s_cfg->CnviBtCore);
/* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */
@@ -611,7 +611,7 @@ static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg,
s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode;
#endif
/* Enable Hybrid storage auto detection */
- s_cfg->HybridStorageMode = config->HybridStorageMode;
+ s_cfg->HybridStorageMode = config->hybrid_storage_mode;
}
static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
@@ -663,7 +663,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
* Boards not needing the optimizers explicitly disables them by setting
* these disable variables to 1 in devicetree overrides.
*/
- s_cfg->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
+ s_cfg->PchPwrOptEnable = !(config->dmi_power_optimize_disable);
s_cfg->PmSupport = 1;
s_cfg->Hwp = 1;
s_cfg->Cx = 1;
@@ -712,10 +712,10 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
power_cycle_duration);
/* Set PsysPmax if it is available from DT */
- if (config->PsysPmax) {
- printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax);
+ if (config->platform_pmax) {
+ printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->platform_pmax);
/* PsysPmax is in unit of 1/8 Watt */
- s_cfg->PsysPmax = config->PsysPmax * 8;
+ s_cfg->PsysPmax = config->platform_pmax * 8;
}
}
@@ -776,19 +776,19 @@ static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
/* transform from Hz to 100 KHz */
- s_cfg->FivrRfiFrequency = config->FivrRfiFrequency / (100 * KHz);
- s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum;
+ s_cfg->FivrRfiFrequency = config->fivr_rfi_frequency / (100 * KHz);
+ s_cfg->FivrSpreadSpectrum = config->fivr_spread_spectrum;
}
static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
- s_cfg->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
+ s_cfg->AcousticNoiseMitigation = config->acoustic_noise_mitigation;
if (s_cfg->AcousticNoiseMitigation) {
for (int i = 0; i < NUM_VR_DOMAINS; i++) {
- s_cfg->FastPkgCRampDisable[i] = config->FastPkgCRampDisable[i];
- s_cfg->SlowSlewRate[i] = config->SlowSlewRate[i];
+ s_cfg->FastPkgCRampDisable[i] = config->fast_pkg_c_ramp_disable[i];
+ s_cfg->SlowSlewRate[i] = config->slow_slew_rate[i];
}
}
}
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 3483abddd7..2a02c21d22 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -115,8 +115,8 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
/* IGD is enabled, set IGD stolen size to 60MB. */
m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB;
/* DP port config */
- m_cfg->DdiPortAConfig = config->DdiPortAConfig;
- m_cfg->DdiPortBConfig = config->DdiPortBConfig;
+ m_cfg->DdiPortAConfig = config->ddi_portA_config;
+ m_cfg->DdiPortBConfig = config->ddi_portB_config;
for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) {
*ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] &
DDI_ENABLE_DDC);
@@ -138,10 +138,10 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_alderlake_config *config)
{
- m_cfg->SaGv = config->SaGv;
+ m_cfg->SaGv = config->sagv;
m_cfg->RMT = config->RMT;
- if (config->MaxDramSpeed)
- m_cfg->DdrFreqLimit = config->MaxDramSpeed;
+ if (config->max_dram_speed)
+ m_cfg->DdrFreqLimit = config->max_dram_speed;
}
static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
@@ -203,7 +203,7 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
m_cfg->LockPTMregs = 0;
/* Skip CPU replacement check */
- m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
+ m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check;
/* Skip GPIO configuration from FSP */
m_cfg->GpioOverride = 0x1;
@@ -223,10 +223,10 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
{
/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
- m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
- m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
- m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
- m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable;
+ m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable;
+ m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
+ m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
+ m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
/*
* All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
* configure GPIO pads for audio. Mainboard is expected to perform all GPIO
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 17:27:22 +0000