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-rw-r--r--src/soc/intel/xeon_sp/cpx/chip.c56
-rw-r--r--src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h4
-rw-r--r--src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h24
-rw-r--r--src/soc/intel/xeon_sp/skx/soc_util.c48
-rw-r--r--src/soc/intel/xeon_sp/spr/chip.c69
-rw-r--r--src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h6
6 files changed, 112 insertions, 95 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 1e84dd5a5c..6274f02f61 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -6,6 +6,7 @@
#include <cpu/x86/mp.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <device/pci_def.h>
#include <gpio.h>
#include <intelblocks/acpi.h>
#include <intelblocks/lpc_lib.h>
@@ -115,33 +116,38 @@ static void iio_enable_masks(void)
static void set_pcu_locks(void)
{
- for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) {
- if (!soc_cpu_is_enabled(socket))
- continue;
- uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
-
- /* configure PCU_CR0_FUN csrs */
- const struct device *cr0_dev = PCU_DEV_CR0(bus);
- pci_or_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK);
- pci_or_config32(cr0_dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, PKG_PWR_LIM_LOCK_UPR);
- pci_or_config32(cr0_dev, PCU_CR0_TURBO_ACTIVATION_RATIO, TURBO_ACTIVATION_RATIO_LOCK);
-
-
- /* configure PCU_CR1_FUN csrs */
- const struct device *cr1_dev = PCU_DEV_CR1(bus);
- pci_or_config32(cr1_dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK);
-
- /* configure PCU_CR2_FUN csrs */
- const struct device *cr2_dev = PCU_DEV_CR2(bus);
- pci_or_config32(cr2_dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, PP_PWR_LIM_LOCK);
- pci_or_config32(cr2_dev, PCU_CR2_DRAM_POWER_INFO_UPR, DRAM_POWER_INFO_LOCK_UPR);
-
- /* configure PCU_CR3_FUN csrs */
- const struct device *cr3_dev = PCU_DEV_CR3(bus);
- pci_or_config32(cr3_dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK);
- pci_or_config32(cr3_dev, PCU_CR3_FLEX_RATIO, OC_LOCK);
+ struct device *dev = NULL;
+
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) {
+ printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+ pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK);
+ pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR,
+ PKG_PWR_LIM_LOCK_UPR);
+ pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO,
+ TURBO_ACTIVATION_RATIO_LOCK);
}
+ dev = NULL;
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) {
+ printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+ pci_or_config32(dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK);
+ }
+
+ dev = NULL;
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) {
+ printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+ pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT,
+ PP_PWR_LIM_LOCK);
+ pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR,
+ DRAM_POWER_INFO_LOCK_UPR);
+ }
+
+ dev = NULL;
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) {
+ printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+ pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK);
+ pci_or_config32(dev, PCU_CR3_FLEX_RATIO, OC_LOCK);
+ }
}
static void set_imc_locks(void)
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 587c97cd8b..614f42af08 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -24,6 +24,7 @@
#define PCU_DEV 30
#define PCU_CR0_FUN 0
+#define PCU_CR0_DEVID 0x344a
#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN)
#define PCU_CR0_PLATFORM_INFO 0xa8
#define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0
@@ -37,6 +38,7 @@
#define PMAX_LOCK BIT(31)
#define PCU_CR1_FUN 1
+#define PCU_CR1_DEVID 0x344b
#define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN)
#define PCU_CR1_BIOS_MB_DATA_REG 0x8c
@@ -64,6 +66,7 @@
#define SAPMCTL_LOCK_MASK BIT(31)
#define PCU_CR2_FUN 2
+#define PCU_CR2_DEVID 0x344c
#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN)
#define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8
#define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4)
@@ -72,6 +75,7 @@
#define PP_PWR_LIM_LOCK BIT(31)
#define PCU_CR3_FUN 3
+#define PCU_CR3_DEVID 0x344d
#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN)
#define PCU_CR3_CONFIG_TDP_CONTROL 0x60
#define TDP_LOCK BIT(31)
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index d317d0c470..8b3c36c7b7 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -9,17 +9,15 @@
#include <hob_iiouds.h>
#include <soc/pch_pci_devs.h>
-#define dump_csr(fmt, dev, reg) \
- printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \
- fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \
- ((uint32_t)dev >> 12) & 0x07, \
- #reg, reg, pci_s_read_config32(dev, reg))
-
-#define dump_csr64(fmt, dev, reg) \
- printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x%x\n", \
- fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \
- ((uint32_t)dev >> 12) & 0x07, #reg, reg, \
- pci_s_read_config32(dev, reg+4), pci_s_read_config32(dev, reg))
+#define dump_csr(dev, reg) \
+ printk(BIOS_SPEW, "%s reg: %s (0x%x), data: 0x%x\n", \
+ dev_path(dev), \
+ #reg, reg, pci_read_config32(dev, reg))
+
+#define dump_csr64(dev, reg) \
+ printk(BIOS_SPEW, "%s reg: %s (0x%x), data: 0x%x%x\n", \
+ dev_path(dev), #reg, reg, \
+ pci_read_config32(dev, reg+4), pci_read_config32(dev, reg))
#define SAD_ALL_DEV 29
#define SAD_ALL_FUNC 0
@@ -36,8 +34,10 @@
#define PCU_IIO_STACK 1
#define PCU_DEV 30
#define PCU_CR1_FUN 1
+#define PCU_CR1_DEVID 0x2081
#define PCU_CR0_FUN 0
+#define PCU_CR0_DEVID 0x2080
#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN)
#define PCU_CR0_PLATFORM_INFO 0xa8
#define PCU_CR0_P_STATE_LIMITS 0xd8
@@ -73,6 +73,8 @@
#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0
#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31)
+#define PCU_CR2_DEVID 0x2082
+
#if !defined(__SIMPLE_DEVICE__)
#define _UBOX_DEV(func) pcidev_path_on_root_debug(PCI_DEVFN(UBOX_DEV, func), __func__)
#else
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index 3e0299956f..4201d10d2c 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -3,6 +3,8 @@
#include <assert.h>
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
#include <hob_iiouds.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pcr.h>
@@ -110,55 +112,55 @@ uint32_t get_socket_ubox_busno(uint32_t socket)
return get_socket_stack_busno(socket, PCU_IIO_STACK);
}
+#if ENV_RAMSTAGE
void config_reset_cpl3_csrs(void)
{
uint32_t data, plat_info, max_min_turbo_limit_ratio;
+ struct device *dev;
- for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) {
- uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
-
- /* configure PCU_CR0_FUN csrs */
- pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN);
- data = pci_s_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS);
+ dev = NULL;
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) {
+ data = pci_read_config32(dev, PCU_CR0_P_STATE_LIMITS);
data |= P_STATE_LIMITS_LOCK;
- pci_s_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data);
+ pci_write_config32(dev, PCU_CR0_P_STATE_LIMITS, data);
- plat_info = pci_s_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO);
- dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO);
+ plat_info = pci_read_config32(dev, PCU_CR0_PLATFORM_INFO);
+ dump_csr64(dev, PCU_CR0_PLATFORM_INFO);
max_min_turbo_limit_ratio =
(plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
MAX_NON_TURBO_LIM_RATIO_SHIFT;
printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n",
plat_info, max_min_turbo_limit_ratio);
+ }
- /* configure PCU_CR1_FUN csrs */
- pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
-
- data = pci_s_read_config32(cr1_dev, PCU_CR1_SAPMCTL);
+ dev = NULL;
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) {
+ data = pci_read_config32(dev, PCU_CR1_SAPMCTL);
/* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
data &= 0x0fffffff;
data |= SAPMCTL_LOCK_MASK;
- pci_s_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data);
-
- /* configure PCU_CR1_FUN csrs */
- pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN);
+ pci_write_config32(dev, PCU_CR1_SAPMCTL, data);
+ }
+ dev = NULL;
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) {
data = PCIE_IN_PKGCSTATE_L1_MASK;
- pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
+ pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
data = KTI_IN_PKGCSTATE_L1_MASK;
- pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
+ pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
data = PROCHOT_RATIO;
printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
- pci_s_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
- dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
+ pci_write_config32(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
+ dump_csr(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
- data = pci_s_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
+ data = pci_read_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
- pci_s_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
+ pci_write_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
}
}
+#endif
/*
* EX: SKX-SP
diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c
index cebe4fe366..d57b240ce3 100644
--- a/src/soc/intel/xeon_sp/spr/chip.c
+++ b/src/soc/intel/xeon_sp/spr/chip.c
@@ -6,6 +6,7 @@
#include <cpu/x86/lapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <device/pci_def.h>
#include <device/pciexp.h>
#include <intelblocks/gpio.h>
#include <intelblocks/lpc_lib.h>
@@ -80,45 +81,41 @@ static void chip_enable_dev(struct device *dev)
}
}
-static void pcu_pci_or_config32(u8 bus, u8 func, u32 reg, u32 orval)
+static void set_pcu_locks(void)
{
- u32 data;
- const uint32_t pcie_offset = PCI_DEV(bus, PCU_DEV, func);
+ struct device *dev = NULL;
+
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) {
+ printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+ pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK);
+ pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR,
+ PKG_PWR_LIM_LOCK_UPR);
+ pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO,
+ TURBO_ACTIVATION_RATIO_LOCK);
+ }
- data = pci_s_read_config32(pcie_offset, reg);
- data |= orval;
- pci_s_write_config32(pcie_offset, reg, data);
-}
+ dev = NULL;
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) {
+ printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+ pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR,
+ DRAM_POWER_INFO_LOCK_UPR);
+ pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR,
+ PP_PWR_LIM_LOCK_UPR);
+ }
-static void set_pcu_locks(void)
-{
- for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) {
- if (!soc_cpu_is_enabled(socket))
- continue;
- const uint32_t bus = get_ubox_busno(socket, UNCORE_BUS_1);
-
- /* configure PCU_CR0_FUN csrs */
- pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_P_STATE_LIMITS,
- P_STATE_LIMITS_LOCK);
- pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR,
- PKG_PWR_LIM_LOCK_UPR);
- pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_TURBO_ACTIVATION_RATIO,
- TURBO_ACTIVATION_RATIO_LOCK);
-
- /* configure PCU_CR2_FUN csrs */
- pcu_pci_or_config32(bus, PCU_CR2_FUN, PCU_CR2_DRAM_POWER_INFO_UPR,
- DRAM_POWER_INFO_LOCK_UPR);
- pcu_pci_or_config32(bus, PCU_CR2_FUN, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR,
- PP_PWR_LIM_LOCK_UPR);
-
- /* configure PCU_CR3_FUN csrs */
- pcu_pci_or_config32(bus, PCU_CR3_FUN, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK);
-
- /* configure PCU_CR6_FUN csrs */
- pcu_pci_or_config32(bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR,
- PLT_PWR_LIM_LOCK_UPR);
- pcu_pci_or_config32(bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR,
- PLT_PWR_INFO_LOCK_UPR);
+ dev = NULL;
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) {
+ printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+ pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK);
+ }
+
+ dev = NULL;
+ while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR6_DEVID, dev))) {
+ printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+ pci_or_config32(dev, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR,
+ PLT_PWR_LIM_LOCK_UPR);
+ pci_or_config32(dev, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR,
+ PLT_PWR_INFO_LOCK_UPR);
}
}
diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
index 158352a8be..1d7dedd82e 100644
--- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
@@ -47,6 +47,7 @@
#define PCU_DEV 30
#define PCU_CR0_FUN 0
+#define PCU_CR0_DEVID 0x3258
#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN)
#define PCU_CR0_PLATFORM_INFO 0xa8
#define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0
@@ -62,6 +63,7 @@
#define VR_CURRENT_CONFIG_LOCK BIT(31)
#define PCU_CR1_FUN 1
+#define PCU_CR1_DEVID 0x3259
#define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN)
#define PCU_CR1_BIOS_MB_DATA_REG 0x8c
@@ -86,6 +88,7 @@
#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31)
#define PCU_CR2_FUN 2
+#define PCU_CR2_DEVID 0x325a
#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN)
#define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8
#define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4)
@@ -96,6 +99,7 @@
#define PP_PWR_LIM_LOCK_UPR BIT(31)
#define PCU_CR3_FUN 3
+#define PCU_CR3_DEVID 0x325b
#define PCU_CR3_CAPID4 0x94
#define ERR_SPOOFING_DIS 1
#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN)
@@ -105,6 +109,7 @@
#define OC_LOCK BIT(20)
#define PCU_CR4_FUN 4
+#define PCU_CR4_DEVID 0x325c
#define PCU_VIRAL_CONTROL 0x84
#define PCU_FW_ERR_EN (1 << 10)
#define PCU_UC_ERR_EN (1 << 9)
@@ -112,6 +117,7 @@
#define PCU_EMCA_MODE (1 << 2)
#define PCU_CR6_FUN 6
+#define PCU_CR6_DEVID 0x325e
#define PCU_DEV_CR6(bus) _PCU_DEV(bus, PCU_CR6_FUN)
#define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR 0xa8
#define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR (PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR + 4)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 08:08:17 +0000