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-rw-r--r--src/soc/qualcomm/common/display/mdss.c (renamed from src/soc/qualcomm/sc7180/display/mdss.c)46
-rw-r--r--src/soc/qualcomm/sc7180/Makefile.inc3
-rw-r--r--src/soc/qualcomm/sc7180/display/disp.c39
-rw-r--r--src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h70
4 files changed, 117 insertions, 41 deletions
diff --git a/src/soc/qualcomm/sc7180/display/mdss.c b/src/soc/qualcomm/common/display/mdss.c
index 95697603cc..1ff923d17b 100644
--- a/src/soc/qualcomm/sc7180/display/mdss.c
+++ b/src/soc/qualcomm/common/display/mdss.c
@@ -2,7 +2,9 @@
#include <device/mmio.h>
#include <console/console.h>
+#include <delay.h>
#include <edid.h>
+#include <soc/clock.h>
#include <soc/display/mdssreg.h>
#define MDSS_MDP_MAX_PREFILL_FETCH 24
@@ -41,7 +43,7 @@ static void mdss_source_pipe_config(struct edid *edid)
write32(&mdp_sspp->sspp_src_format, 0x000236ff);
write32(&mdp_sspp->sspp_src_unpack_pattern, 0x03020001);
- flip_bits |= BIT(31);
+ flip_bits |= SW_PIX_EXT_OVERRIDE;
write32(&mdp_sspp->sspp_sw_pic_ext_c0_req_pixels, out_size);
write32(&mdp_sspp->sspp_sw_pic_ext_c1c2_req_pixels, out_size);
write32(&mdp_sspp->sspp_sw_pic_ext_c3_req_pixels, out_size);
@@ -54,38 +56,11 @@ static void mdss_vbif_setup(void)
write32(&vbif_rt->vbif_out_axi_amemtype_conf1, 0x00333333);
}
-static void mdss_intf_tg_setup(struct edid *edid)
-{
- uint32_t hsync_period, vsync_period;
- uint32_t hsync_start_x, hsync_end_x;
- uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
-
- hsync_period = edid->mode.ha + edid->mode.hbl;
- vsync_period = edid->mode.va + edid->mode.vbl;
- hsync_start_x = edid->mode.hbl - edid->mode.hso;
- hsync_end_x = hsync_period - edid->mode.hso - 1;
- display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period;
- display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1;
- hsync_ctl = (hsync_period << 16) | edid->mode.hspw;
- display_hctl = (hsync_end_x << 16) | hsync_start_x;
-
- write32(&mdp_intf->intf_hsync_ctl, hsync_ctl);
- write32(&mdp_intf->intf_vysnc_period_f0,
- vsync_period * hsync_period);
- write32(&mdp_intf->intf_vysnc_pulse_width_f0,
- edid->mode.vspw * hsync_period);
- write32(&mdp_intf->intf_disp_hctl, display_hctl);
- write32(&mdp_intf->intf_disp_v_start_f0, display_vstart);
- write32(&mdp_intf->intf_disp_v_end_f0, display_vend);
- write32(&mdp_intf->intf_underflow_color, 0x00);
- write32(&mdp_intf->intf_panel_format, 0x2100);
-}
-
static void mdss_intf_fetch_start_config(struct edid *edid)
{
uint32_t v_total, h_total, fetch_start, vfp_start;
uint32_t prefetch_avail, prefetch_needed;
- uint32_t fetch_enable = BIT(31);
+ uint32_t fetch_enable = PROG_FETCH_START_EN;
/*
* MDP programmable fetch is for MDP with rev >= 1.05.
@@ -135,8 +110,8 @@ static void mdss_layer_mixer_setup(struct edid *edid)
}
/* Enable border fill */
- left_staging_level = BIT(24);
- left_staging_level |= BIT(1);
+ left_staging_level = BORDER_OUT;
+ left_staging_level |= VIG_0_OUT;
/* Base layer for layer mixer 0 */
write32(&mdp_ctl->ctl_layer0, left_staging_level);
@@ -172,12 +147,7 @@ void mdp_dsi_video_config(struct edid *edid)
mdss_vbif_qos_remapper_setup();
mdss_source_pipe_config(edid);
mdss_layer_mixer_setup(edid);
-
- /* Select Video Mode Interface */
- write32(&mdp_ctl->ctl_top, 0x0);
-
- /* PPB0 to INTF1 */
- write32(&mdp_ctl->ctl_intf_active, BIT(1));
+ mdss_ctrl_config();
write32(&mdp_intf->intf_mux, 0x0F0000);
}
@@ -186,6 +156,6 @@ void mdp_dsi_video_on(void)
uint32_t ctl0_reg_val;
ctl0_reg_val = VIG_0 | LAYER_MIXER_0 | CTL | INTF;
- write32(&mdp_ctl->ctl_intf_flush, 0x2);
+ write32(&mdp_ctl->ctl_intf_flush, INTF_FLUSH);
write32(&mdp_ctl->ctl_flush, ctl0_reg_val);
}
diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc
index c8d7f2f78d..262abfa392 100644
--- a/src/soc/qualcomm/sc7180/Makefile.inc
+++ b/src/soc/qualcomm/sc7180/Makefile.inc
@@ -45,7 +45,8 @@ ramstage-y += ../common/usb/qmpv3_usb_phy.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/mdss.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/disp.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/display/mdss.c
################################################################################
diff --git a/src/soc/qualcomm/sc7180/display/disp.c b/src/soc/qualcomm/sc7180/display/disp.c
new file mode 100644
index 0000000000..4ee6bec4ac
--- /dev/null
+++ b/src/soc/qualcomm/sc7180/display/disp.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/display/mdssreg.h>
+
+void mdss_intf_tg_setup(struct edid *edid)
+{
+ uint32_t hsync_period, vsync_period, hsync_start_x, hsync_end_x;
+ uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
+ uint32_t mdss_version;
+
+ mdss_version = read32(&mdss_hw->hw_version);
+ hsync_period = edid->mode.ha + edid->mode.hbl;
+ vsync_period = edid->mode.va + edid->mode.vbl;
+ hsync_start_x = edid->mode.hbl - edid->mode.hso;
+ hsync_end_x = hsync_period - edid->mode.hso - 1;
+ display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period;
+ display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1;
+ hsync_ctl = (hsync_period << 16) | edid->mode.hspw;
+ display_hctl = (hsync_end_x << 16) | hsync_start_x;
+
+ write32(&mdp_intf->intf_hsync_ctl, hsync_ctl);
+ write32(&mdp_intf->intf_vysnc_period_f0, vsync_period * hsync_period);
+ write32(&mdp_intf->intf_vysnc_pulse_width_f0, edid->mode.vspw * hsync_period);
+ write32(&mdp_intf->intf_disp_hctl, display_hctl);
+ write32(&mdp_intf->intf_disp_v_start_f0, display_vstart);
+ write32(&mdp_intf->intf_disp_v_end_f0, display_vend);
+ write32(&mdp_intf->intf_underflow_color, 0x00);
+ write32(&mdp_intf->intf_panel_format, 0x2100);
+}
+
+void mdss_ctrl_config(void)
+{
+ /* Select Video Mode Interface */
+ write32(&mdp_ctl->ctl_top, 0x0);
+
+ /* PPB0 to INTF1 */
+ write32(&mdp_ctl->ctl_intf_active, INTF_ACTIVE_1);
+}
diff --git a/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h
index 112cac67fb..87b36a11e8 100644
--- a/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h
+++ b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h
@@ -4,6 +4,9 @@
#define _SOC_DISPLAY_MDSS_REG_H_
#include <types.h>
+#include <edid.h>
+
+#define INTF_FLUSH INTF_FLUSH_1
struct dsi_regs {
uint32_t hw_version;
@@ -235,7 +238,14 @@ struct mdp_intf_regs {
uint32_t intf_active_hctl;
uint32_t intf_border_color;
uint32_t intf_underflow_color;
- uint32_t reserved0[17];
+ uint32_t hsync_skew;
+ uint32_t polarity_ctl;
+ uint32_t test_ctl;
+ uint32_t tp_color0;
+ uint32_t tp_color1;
+ uint32_t intf_config2;
+ uint32_t display_data_hctl;
+ uint32_t reserved0[10];
uint32_t intf_panel_format;
uint32_t reserved1[55];
uint32_t intf_prof_fetch_start;
@@ -256,7 +266,9 @@ struct mdp_ctl_regs {
uint32_t ctl_start;
uint32_t reserved1[53];
uint32_t ctl_intf_active;
- uint32_t reserved2[6];
+ uint32_t ctl_cdm_active;
+ uint32_t ctl_fetch_pipe_active; /* reserved for sc7180 */
+ uint32_t reserved2[4];
uint32_t ctl_intf_flush;
};
@@ -308,6 +320,10 @@ check_member(mdp_sspp_regs, sspp_sw_pic_ext_c0_req_pixels, 0x108);
check_member(mdp_sspp_regs, sspp_sw_pic_ext_c1c2_req_pixels, 0x118);
check_member(mdp_sspp_regs, sspp_sw_pic_ext_c3_req_pixels, 0x128);
+struct mdss_hw_regs {
+ uint32_t hw_version;
+};
+
struct vbif_rt_regs {
uint32_t reserved0[88];
uint32_t vbif_out_axi_amemtype_conf0;
@@ -448,9 +464,57 @@ enum {
BROADCAST_EN = BIT(31),
};
+/* MDP_VP_0_VIG_0_SSPP_SRC_OP_MODE */
+enum {
+ BWC_DEC_EN = BIT(0),
+ SW_PIX_EXT_OVERRIDE = BIT(31),
+
+};
+
+/* MDP_INTF_x_INTF_CONFIG */
+enum {
+ INTERLACE_MODE = BIT(0),
+ REPEAT_PIXEL = BIT(1),
+ INTERLACE_INIT_SEL = BIT(2),
+ BORDER_ENABLE = BIT(3),
+ EDP_PSR_OVERRIDE_EN = BIT(7),
+ PACK_ALIGN = BIT(10),
+ DSI_VIDEO_STOP_MODE = BIT(23),
+ ACTIVE_H_EN = BIT(29),
+ ACTIVE_V_EN = BIT(30),
+ PROG_FETCH_START_EN = BIT(31),
+};
+
+/* MDP_CTL_0_LAYER_0 */
+enum {
+ VIG_0_OUT = BIT(0),
+ BORDER_OUT = BIT(24),
+};
+
+/* MDP_CTL_0_FETCH_PIPE_ACTIVE */
+enum {
+ FETCH_PIPE_VIG0_ACTIVE = BIT(16),
+ FETCH_PIPE_VIG1_ACTIVE = BIT(17),
+};
+
+/* MDP_CTL_0_INTF_ACTIVE*/
+enum {
+ INTF_ACTIVE_0 = BIT(0),
+ INTF_ACTIVE_1 = BIT(1),
+ INTF_ACTIVE_5 = BIT(5),
+};
+
+/* MDP_CTL_0_INTF_FLUSH */
+enum {
+ INTF_FLUSH_0 = BIT(0),
+ INTF_FLUSH_1 = BIT(1),
+ INTF_FLUSH_5 = BIT(5),
+};
+
static struct dsi_regs *const dsi0 = (void *)DSI0_CTL_BASE;
static struct dsi_phy_regs *const dsi0_phy = (void *)DSI0_PHY_BASE;
static struct dsi_phy_pll_qlink_regs *const phy_pll_qlink = (void *)DSI0_PHY_PLL_QLINK_COM;
+static struct mdss_hw_regs *const mdss_hw = (void *)MDSS_BASE;
static struct mdp_intf_regs *const mdp_intf = (void *)MDP_1_INTF_BASE;
static struct mdp_ctl_regs *const mdp_ctl = (void *)MDP_0_CTL_BASE;
static struct mdp_layer_mixer_regs *const mdp_layer_mixer = (void *)MDP_VP_0_LAYER_MIXER_BASE;
@@ -458,6 +522,8 @@ static struct mdp_sspp_regs *const mdp_sspp = (void *)MDP_VP_0_SSPP_BASE;
static struct vbif_rt_regs *const vbif_rt = (void *)MDP_VBIF_RT_BASE;
void mdp_dsi_video_config(struct edid *edid);
+void mdss_intf_tg_setup(struct edid *edid);
void mdp_dsi_video_on(void);
+void mdss_ctrl_config(void);
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 19:31:42 +0000