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-rw-r--r--src/soc/intel/alderlake/fsp_params.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 5346403705..dda2145358 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1068,6 +1068,15 @@ static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
s_cfg->PchFivrExtVnnRailIccMaximum =
config->ext_fivr_settings.vnn_icc_max_ma;
+
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
+ /* Enable the FIVR VCCST ICCMax Control for ADL-N.
+ * TODO:Right now the UPD is update in partial headers for only ADL-N and when its
+ * updated for ADL-P then we will remove the config since this needs to be enabled for
+ * all the Alderlake platforms.
+ */
+ s_cfg->PchFivrVccstIccMaxControl = 1;
+#endif
}
static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,