2 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c
index 5b226407c7..f3a9ceee21 100644
--- a/src/soc/imgtec/pistachio/clocks.c
+++ b/src/soc/imgtec/pistachio/clocks.c
@@ -98,6 +98,12 @@
 #define UART1CLKOUT_CTRL_ADDR		0xB8144240
 #define UART1CLKOUT_MASK		0x000003FF
 
+/* Definitions for I2C0 setup */
+#define I2C0CLKDIV1_CTRL_ADDR		0xB814413C
+#define I2C0CLKDIV1_MASK		0x0000007F
+#define I2C0CLKOUT_CTRL_ADDR		0xB8144140
+#define I2C0CLKOUT_MASK			0x0000007F
+
 /* Definitions for ROM clock setup */
 #define ROMCLKOUT_CTRL_ADDR		0xB814490C
 #define ROMCLKOUT_MASK			0x0000007F
@@ -300,6 +306,32 @@ void uart1_clk_setup(u8 divider1, u16 divider2)
 	write32(UART1CLKOUT_CTRL_ADDR, reg);
 }
 
+/*
+ * i2c_clk_setup: sets up clocks for I2C0
+ * divider1: 7-bit divider value
+ * divider2: 7-bit divider value
+ */
+void i2c0_clk_setup(u8 divider1, u16 divider2)
+{
+	u32 reg;
+
+	/* Check input parameters */
+	assert(!(divider1 & ~(I2C0CLKDIV1_MASK)));
+	assert(!(divider2 & ~(I2C0CLKOUT_MASK)));
+
+	/* Set divider 1 */
+	reg = read32(I2C0CLKDIV1_CTRL_ADDR);
+	reg &= ~I2C0CLKDIV1_MASK;
+	reg |= divider1 & I2C0CLKDIV1_MASK;
+	write32(I2C0CLKDIV1_CTRL_ADDR, reg);
+
+	/* Set divider 2 */
+	reg = read32(I2C0CLKOUT_CTRL_ADDR);
+	reg &= ~I2C0CLKOUT_MASK;
+	reg |= divider2 & I2C0CLKOUT_MASK;
+	write32(I2C0CLKOUT_CTRL_ADDR, reg);
+}
+
 /* system_clk_setup: sets up the system (peripheral) clock */
 void system_clk_setup(u8 divider)
 {
diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h
index f57d43d89e..81b640ebbd 100644
--- a/src/soc/imgtec/pistachio/include/soc/clocks.h
+++ b/src/soc/imgtec/pistachio/include/soc/clocks.h
@@ -28,6 +28,7 @@ int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback);
 void system_clk_setup(u8 divider);
 void mips_clk_setup(u8 divider1, u8 divider2);
 void uart1_clk_setup(u8 divider1, u16 divider2);
+void i2c0_clk_setup(u8 divider1, u16 divider2);
 int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel);
 void rom_clk_setup(u8 divider);
 void eth_clk_setup(u8 mux, u8 divider);