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-rw-r--r--src/soc/intel/common/block/smm/Kconfig7
-rw-r--r--src/soc/intel/common/block/smm/smihandler.c4
-rw-r--r--src/soc/intel/common/block/smm/smm.c16
3 files changed, 9 insertions, 18 deletions
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig
index cc6bc44f58..a58c63102d 100644
--- a/src/soc/intel/common/block/smm/Kconfig
+++ b/src/soc/intel/common/block/smm/Kconfig
@@ -8,13 +8,12 @@ config SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
help
Intel Processor trap flag if it is supported
-config SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS
+config SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
bool
default n
help
- Disable eSPI SMI when ACPI mode is enabled. This will
- prevent the embedded controller from asserting SMI when
- booted into an ACPI aware OS.
+ Disable eSPI SMI source to prevent the embedded controller
+ from asserting SMI while in firmware.
config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS
int
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 16bb3a2d1d..7aa69c5c65 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -361,14 +361,10 @@ void smihandler_southbridge_apmc(
break;
case APM_CNT_ACPI_DISABLE:
pmc_disable_pm1_control(SCI_EN);
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
- pmc_enable_smi(ESPI_SMI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case APM_CNT_ACPI_ENABLE:
pmc_enable_pm1_control(SCI_EN);
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
- pmc_disable_smi(ESPI_SMI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
case APM_CNT_GNVS_UPDATE:
diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c
index dd8bab3483..75b933e0e9 100644
--- a/src/soc/intel/common/block/smm/smm.c
+++ b/src/soc/intel/common/block/smm/smm.c
@@ -41,6 +41,8 @@ void smm_southbridge_clear_state(void)
void smm_southbridge_enable(uint16_t pm1_events)
{
+ uint32_t smi_params = ENABLE_SMI_PARAMS;
+
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events */
pmc_enable_pm1(pm1_events);
@@ -60,14 +62,16 @@ void smm_southbridge_enable(uint16_t pm1_events)
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
- * - on eSPI events (does nothing on LPC systems)
+ * - on eSPI events, unless disabled (does nothing on LPC systems)
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
* - on TCO events
*/
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE))
+ smi_params &= ~ESPI_SMI_EN;
/* Enable SMI generation: */
- pmc_enable_smi(ENABLE_SMI_PARAMS);
+ pmc_enable_smi(smi_params);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
@@ -94,11 +98,3 @@ void smm_region_info(void **start, size_t *size)
*start = (void *)sa_get_tseg_base();
*size = sa_get_tseg_size();
}
-
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)
-static void smm_disable_espi(void *dest)
-{
- pmc_disable_smi(ESPI_SMI_EN);
-}
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, smm_disable_espi, NULL);
-#endif