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-rw-r--r--src/soc/amd/picasso/acpi.c6
-rw-r--r--src/soc/amd/picasso/acpi/cpu.asl22
-rw-r--r--src/soc/amd/picasso/southbridge.c2
-rw-r--r--src/soc/amd/stoneyridge/acpi.c6
-rw-r--r--src/soc/amd/stoneyridge/acpi/cpu.asl30
-rw-r--r--src/soc/amd/stoneyridge/northbridge.c17
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c2
7 files changed, 51 insertions, 34 deletions
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index e8bbf57fab..8ee7c97b6c 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -236,13 +236,13 @@ void generate_cpu_entries(struct device *device)
int cores, cpu;
cores = get_cpu_count();
- printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
+ printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores);
- /* Generate BSP \_PR.P000 */
+ /* Generate BSP \_SB.P000 */
acpigen_write_processor(0, ACPI_GPE0_BLK, 6);
acpigen_pop_len();
- /* Generate AP \_PR.Pxxx */
+ /* Generate AP \_SB.Pxxx */
for (cpu = 1; cpu < cores; cpu++) {
acpigen_write_processor(cpu, 0, 0);
acpigen_pop_len();
diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl
index 59ac62e1ec..587dbea18c 100644
--- a/src/soc/amd/picasso/acpi/cpu.asl
+++ b/src/soc/amd/picasso/acpi/cpu.asl
@@ -21,14 +21,14 @@ Method (PNOT)
* Processor Object
*/
/* These devices are created at runtime */
-External (\_PR.P000, DeviceObj)
-External (\_PR.P001, DeviceObj)
-External (\_PR.P002, DeviceObj)
-External (\_PR.P003, DeviceObj)
-External (\_PR.P004, DeviceObj)
-External (\_PR.P005, DeviceObj)
-External (\_PR.P006, DeviceObj)
-External (\_PR.P007, DeviceObj)
+External (\_SB.P000, DeviceObj)
+External (\_SB.P001, DeviceObj)
+External (\_SB.P002, DeviceObj)
+External (\_SB.P003, DeviceObj)
+External (\_SB.P004, DeviceObj)
+External (\_SB.P005, DeviceObj)
+External (\_SB.P006, DeviceObj)
+External (\_SB.P007, DeviceObj)
/* Return a package containing enabled processor entries */
Method (PPKG)
@@ -36,13 +36,13 @@ Method (PPKG)
If (LGreaterEqual (\PCNT, 2)) {
Return (Package ()
{
- \_PR.P000,
- \_PR.P001
+ \_SB.P000,
+ \_SB.P001
})
} Else {
Return (Package ()
{
- \_PR.P000
+ \_SB.P000
})
}
}
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 1894bea418..61c7f36c07 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -367,7 +367,7 @@ static void sb_init_acpi_ports(void)
pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
- /* CpuControl is in \_PR.CP00, 6 bytes */
+ /* CpuControl is in \_SB.CP00, 6 bytes */
cst_addr.hi = 0;
cst_addr.lo = ACPI_CPU_CONTROL;
wrmsr(CSTATE_BASE_REG, cst_addr);
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 01849b85a0..f59aeb504a 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -241,13 +241,13 @@ void generate_cpu_entries(struct device *device)
cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
cores++; /* number of cores is CmpCap+1 */
- printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
+ printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores);
- /* Generate BSP \_PR.P000 */
+ /* Generate BSP \_SB.P000 */
acpigen_write_processor(0, ACPI_GPE0_BLK, 6);
acpigen_pop_len();
- /* Generate AP \_PR.Pxxx */
+ /* Generate AP \_SB.Pxxx */
for (cpu = 1; cpu < cores; cpu++) {
acpigen_write_processor(cpu, 0, 0);
acpigen_pop_len();
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl
index f52d230bf2..1ecde23f7a 100644
--- a/src/soc/amd/stoneyridge/acpi/cpu.asl
+++ b/src/soc/amd/stoneyridge/acpi/cpu.asl
@@ -21,14 +21,14 @@ Method (PNOT)
* Processor Object
*/
/* These devices are created at runtime */
-External (\_PR.P000, DeviceObj)
-External (\_PR.P001, DeviceObj)
-External (\_PR.P002, DeviceObj)
-External (\_PR.P003, DeviceObj)
-External (\_PR.P004, DeviceObj)
-External (\_PR.P005, DeviceObj)
-External (\_PR.P006, DeviceObj)
-External (\_PR.P007, DeviceObj)
+External (\_SB.P000, DeviceObj)
+External (\_SB.P001, DeviceObj)
+External (\_SB.P002, DeviceObj)
+External (\_SB.P003, DeviceObj)
+External (\_SB.P004, DeviceObj)
+External (\_SB.P005, DeviceObj)
+External (\_SB.P006, DeviceObj)
+External (\_SB.P007, DeviceObj)
/* Return a package containing enabled processor entries */
Method (PPKG)
@@ -36,21 +36,21 @@ Method (PPKG)
If (LGreaterEqual (\PCNT, 4)) {
Return (Package ()
{
- \_PR.P000,
- \_PR.P001,
- \_PR.P002,
- \_PR.P003
+ \_SB.P000,
+ \_SB.P001,
+ \_SB.P002,
+ \_SB.P003
})
} ElseIf (LGreaterEqual (\PCNT, 2)) {
Return (Package ()
{
- \_PR.P000,
- \_PR.P001
+ \_SB.P000,
+ \_SB.P001
})
} Else {
Return (Package ()
{
- \_PR.P000
+ \_SB.P000
})
}
}
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index afe7cf0420..3707049130 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -227,6 +227,22 @@ static void northbridge_fill_ssdt_generator(struct device *device)
acpigen_pop_len();
}
+static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
+{
+ unsigned int len = ssdt->length - sizeof(acpi_header_t);
+ unsigned int i;
+
+ for (i = sizeof(acpi_header_t); i < len; i++) {
+ /* Search for _PR_ scope and replace it with _SB_ */
+ if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
+ *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
+ }
+ /* Recalculate checksum */
+ ssdt->checksum = 0;
+ ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+}
+
+
static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
@@ -322,6 +338,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
if (ssdt != NULL) {
+ patch_ssdt_processor_scope(ssdt);
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *)current;
current += ssdt->length;
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 71b2d90a2c..b636c26699 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -488,7 +488,7 @@ static void sb_init_acpi_ports(void)
pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
- /* CpuControl is in \_PR.CP00, 6 bytes */
+ /* CpuControl is in \_SB.CP00, 6 bytes */
pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
if (CONFIG(HAVE_SMI_HANDLER)) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 16:06:11 +0000