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-rw-r--r--src/soc/intel/baytrail/acpi/globalnvs.asl1
-rw-r--r--src/soc/intel/baytrail/include/soc/nvs.h3
-rw-r--r--src/soc/intel/quark/include/soc/nvs.h4
3 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index cffb2241f0..c73b7a7b3f 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -25,6 +25,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TLVL, 8, /* 0x13 - Throttle Level */
PPCM, 8, /* 0x14 - Maximum P-state usable by OS */
PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */
+ GPEI, 32, /* 0x19 - GPE Wake Source */
/* Device Config */
Offset (0x20),
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 9fb0822b9b..a068d1edd4 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -25,7 +25,8 @@ struct __packed global_nvs {
u8 tlvl; /* 0x13 - Throttle Level */
u8 ppcm; /* 0x14 - Maximum P-state usable by OS */
u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */
- u8 rsvd1[7];
+ u32 gpei; /* 0x19 - GPE Wake Source */
+ u8 rsvd1[3];
/* Device Config */
u8 s5u0; /* 0x20 - Enable USB0 in S5 */
diff --git a/src/soc/intel/quark/include/soc/nvs.h b/src/soc/intel/quark/include/soc/nvs.h
index fee0e42a7d..64378cce3d 100644
--- a/src/soc/intel/quark/include/soc/nvs.h
+++ b/src/soc/intel/quark/include/soc/nvs.h
@@ -8,6 +8,10 @@
struct __packed global_nvs {
uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
uint8_t pwrs; /* 0x4 - Power state (AC = 1) */
+
+ /* Required for future unified acpi_save_wake_source. */
+ uint32_t pm1i;
+ uint32_t gpei;
};
#endif /* SOC_INTEL_QUARK_NVS_H */