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-rw-r--r--src/soc/intel/broadwell/cpu.c7
-rw-r--r--src/soc/intel/broadwell/romstage/report_platform.c15
-rw-r--r--src/soc/intel/cannonlake/bootblock/report_platform.c15
-rw-r--r--src/soc/intel/cannonlake/cpu.c7
-rw-r--r--src/soc/intel/common/block/vmx/vmx.c8
-rw-r--r--src/soc/intel/icelake/bootblock/report_platform.c15
-rw-r--r--src/soc/intel/icelake/cpu.c7
-rw-r--r--src/soc/intel/quark/romstage/report_platform.c9
-rw-r--r--src/soc/intel/skylake/bootblock/report_platform.c15
-rw-r--r--src/soc/intel/skylake/cpu.c7
10 files changed, 57 insertions, 48 deletions
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 2f9f78f69e..ec8f7f30a8 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -19,6 +19,7 @@
#include <device/pci.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/cpu.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
@@ -498,12 +499,12 @@ static void enable_lapic_tpr(void)
static void configure_dca_cap(void)
{
- struct cpuid_result cpuid_regs;
+ uint32_t feature_flag;
msr_t msr;
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
- cpuid_regs = cpuid(1);
- if (cpuid_regs.ecx & (1 << 18)) {
+ feature_flag = cpu_get_feature_flags_ecx();
+ if (feature_flag & CPUID_DCA) {
msr = rdmsr(IA32_PLATFORM_DCA_CAP);
msr.lo |= 1;
wrmsr(IA32_PLATFORM_DCA_CAP, msr);
diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c
index 44a3d2714c..db4b2ebdc5 100644
--- a/src/soc/intel/broadwell/romstage/report_platform.c
+++ b/src/soc/intel/broadwell/romstage/report_platform.c
@@ -86,7 +86,7 @@ static struct {
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
- u32 i, index;
+ u32 i, index, cpu_id, cpu_feature_flag;
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
@@ -114,12 +114,12 @@ static void report_cpu_info(void)
microcode_ver.lo = 0;
microcode_ver.hi = 0;
wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
- cpuidr = cpuid(1);
+ cpu_id = cpu_get_cpuid();
microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
- if (cpu_table[i].cpuid == cpuidr.eax) {
+ if (cpu_table[i].cpuid == cpu_id) {
cpu_type = cpu_table[i].name;
break;
}
@@ -127,11 +127,12 @@ static void report_cpu_info(void)
printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
- cpuidr.eax, cpu_type, microcode_ver.hi);
+ cpu_id, cpu_type, microcode_ver.hi);
- aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
- txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
- vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+ cpu_feature_flag = cpu_get_feature_flags_ecx();
+ aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
+ txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
+ vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, "
"VT %ssupported\n", mode[aes], mode[txt], mode[vt]);
}
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index 17bcce9822..8839816591 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -96,7 +96,7 @@ static uint16_t get_dev_id(pci_devfn_t dev)
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
- u32 i, index;
+ u32 i, index, cpu_id, cpu_feature_flag;
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
@@ -128,12 +128,12 @@ static void report_cpu_info(void)
microcode_ver.lo = 0;
microcode_ver.hi = 0;
wrmsr(BIOS_SIGN_ID, microcode_ver);
- cpuidr = cpuid(1);
+ cpu_id = cpu_get_cpuid();
microcode_ver = rdmsr(BIOS_SIGN_ID);
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
- if (cpu_table[i].cpuid == cpuidr.eax) {
+ if (cpu_table[i].cpuid == cpu_id) {
cpu_type = cpu_table[i].name;
break;
}
@@ -141,11 +141,12 @@ static void report_cpu_info(void)
printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
- cpuidr.eax, cpu_type, microcode_ver.hi);
+ cpu_id, cpu_type, microcode_ver.hi);
- aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
- txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
- vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+ cpu_feature_flag = cpu_get_feature_flags_ecx();
+ aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
+ txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
+ vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_DEBUG,
"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index ccd1deaeff..fe34d05060 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
#include <console/console.h>
#include <device/pci.h>
#include <chip.h>
@@ -104,12 +105,12 @@ static void enable_lapic_tpr(void)
static void configure_dca_cap(void)
{
- struct cpuid_result cpuid_regs;
+ uint32_t feature_flag;
msr_t msr;
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
- cpuid_regs = cpuid(1);
- if (cpuid_regs.ecx & (1 << 18)) {
+ feature_flag = cpu_get_feature_flags_ecx();
+ if (feature_flag & CPUID_DCA) {
msr = rdmsr(IA32_PLATFORM_DCA_CAP);
msr.lo |= 1;
wrmsr(IA32_PLATFORM_DCA_CAP, msr);
diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c
index 2cffdabd2e..d0086d080e 100644
--- a/src/soc/intel/common/block/vmx/vmx.c
+++ b/src/soc/intel/common/block/vmx/vmx.c
@@ -11,8 +11,10 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
+#include <intelblocks/cpulib.h>
#include <intelblocks/msr.h>
#include <intelblocks/vmx.h>
#include <soc/cpu.h>
@@ -46,11 +48,11 @@ static int soc_vmx_enabled(void)
void vmx_configure(void *unused)
{
msr_t msr;
- struct cpuid_result regs;
+ uint32_t feature_flag;
- regs = cpuid(1);
+ feature_flag = cpu_get_feature_flags_ecx();
- if (!soc_vmx_enabled() || !(regs.ecx & CPUID_VMX)) {
+ if (!soc_vmx_enabled() || !(feature_flag & CPUID_VMX)) {
printk(BIOS_ERR, "VMX: pre-conditions not met\n");
return;
}
diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c
index a5dcd7706c..05ae25fcc9 100644
--- a/src/soc/intel/icelake/bootblock/report_platform.c
+++ b/src/soc/intel/icelake/bootblock/report_platform.c
@@ -92,7 +92,7 @@ static uint16_t get_dev_id(pci_devfn_t dev)
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
- u32 i, index;
+ u32 i, index, cpu_id, cpu_feature_flag;
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
@@ -124,12 +124,12 @@ static void report_cpu_info(void)
microcode_ver.lo = 0;
microcode_ver.hi = 0;
wrmsr(BIOS_SIGN_ID, microcode_ver);
- cpuidr = cpuid(1);
+ cpu_id = cpu_get_cpuid();
microcode_ver = rdmsr(BIOS_SIGN_ID);
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
- if (cpu_table[i].cpuid == cpuidr.eax) {
+ if (cpu_table[i].cpuid == cpu_id) {
cpu_type = cpu_table[i].name;
break;
}
@@ -137,11 +137,12 @@ static void report_cpu_info(void)
printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
- cpuidr.eax, cpu_type, microcode_ver.hi);
+ cpu_id, cpu_type, microcode_ver.hi);
- aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
- txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
- vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+ cpu_feature_flag = cpu_get_feature_flags_ecx();
+ aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
+ txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
+ vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_DEBUG,
"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index bfe9f7beb9..0585450214 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
#include <console/console.h>
#include <device/pci.h>
#include <chip.h>
@@ -105,12 +106,12 @@ static void enable_lapic_tpr(void)
static void configure_dca_cap(void)
{
- struct cpuid_result cpuid_regs;
+ uint32_t feature_flag;
msr_t msr;
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
- cpuid_regs = cpuid(1);
- if (cpuid_regs.ecx & (1 << 18)) {
+ feature_flag = cpu_get_feature_flags_ecx();
+ if (feature_flag & CPUID_DCA) {
msr = rdmsr(IA32_PLATFORM_DCA_CAP);
msr.lo |= 1;
wrmsr(IA32_PLATFORM_DCA_CAP, msr);
diff --git a/src/soc/intel/quark/romstage/report_platform.c b/src/soc/intel/quark/romstage/report_platform.c
index 5ed8a5f9cb..640f5b0594 100644
--- a/src/soc/intel/quark/romstage/report_platform.c
+++ b/src/soc/intel/quark/romstage/report_platform.c
@@ -67,14 +67,13 @@ static uint32_t fuse_port_read(uint32_t offset)
static void report_cpu_info(void)
{
- struct cpuid_result cpuidr;
const char *cpu_type = "Unknown";
u32 d_variant;
u32 ecc_enabled;
u32 extended_temp;
u32 i;
u8 revision;
- u32 secure_boot;
+ u32 secure_boot, cpu_id;
const char *stepping = "Unknown";
/* Determine if ECC is enabled */
@@ -94,9 +93,9 @@ static void report_cpu_info(void)
extended_temp = 0;
/* Look for string to match the CPU ID value */
- cpuidr = cpuid(1);
+ cpu_id = cpu_get_cpuid();
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
- if ((cpu_table[i].cpuid == cpuidr.eax)
+ if ((cpu_table[i].cpuid == cpu_id)
&& (cpu_table[i].extended_temp == extended_temp)
&& (cpu_table[i].ecc == ecc_enabled)
&& (cpu_table[i].secure_boot == secure_boot)
@@ -118,7 +117,7 @@ static void report_cpu_info(void)
}
}
- printk(BIOS_DEBUG, "CPU: ID %x:%x, %s %s Stepping\n", cpuidr.eax,
+ printk(BIOS_DEBUG, "CPU: ID %x:%x, %s %s Stepping\n", cpu_id,
revision, cpu_type, stepping);
}
diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index 7dbd371f1a..c245523947 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -121,7 +121,7 @@ static uint16_t get_dev_id(pci_devfn_t dev)
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
- u32 i, index;
+ u32 i, index, cpu_id, cpu_feature_flag;
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
@@ -149,12 +149,12 @@ static void report_cpu_info(void)
microcode_ver.lo = 0;
microcode_ver.hi = 0;
wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
- cpuidr = cpuid(1);
+ cpu_id = cpu_get_cpuid();
microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
- if (cpu_table[i].cpuid == cpuidr.eax) {
+ if (cpu_table[i].cpuid == cpu_id) {
cpu_type = cpu_table[i].name;
break;
}
@@ -162,11 +162,12 @@ static void report_cpu_info(void)
printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
- cpuidr.eax, cpu_type, microcode_ver.hi);
+ cpu_id, cpu_type, microcode_ver.hi);
- aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
- txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
- vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+ cpu_feature_flag = cpu_get_feature_flags_ecx();
+ aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
+ txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
+ vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_DEBUG,
"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 9e4bbe8d4c..9a7315f879 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -16,6 +16,7 @@
*/
#include <assert.h>
+#include <arch/cpu.h>
#include <bootstate.h>
#include <console/console.h>
#include <device/device.h>
@@ -333,12 +334,12 @@ static void enable_lapic_tpr(void)
static void configure_dca_cap(void)
{
- struct cpuid_result cpuid_regs;
+ uint32_t feature_flag;
msr_t msr;
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
- cpuid_regs = cpuid(1);
- if (cpuid_regs.ecx & (1 << 18)) {
+ feature_flag = cpu_get_feature_flags_ecx();
+ if (feature_flag & CPUID_DCA) {
msr = rdmsr(IA32_PLATFORM_DCA_CAP);
msr.lo |= 1;
wrmsr(IA32_PLATFORM_DCA_CAP, msr);
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 04:50:57 +0000