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-rw-r--r--src/soc/intel/baytrail/romstage/cache_as_ram.inc4
-rw-r--r--src/soc/intel/broadwell/romstage/cache_as_ram.inc4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
index 7c6a67faff..583ec5812b 100644
--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc
+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
@@ -82,7 +82,7 @@ wait_for_sipi:
/* Zero out all fixed range and variable range MTRRs. */
movl $fixed_mtrr_table, %esi
- movl $((fixed_mtrr_table_end - fixed_mtrr_table) / 2), %edi
+ movl $((fixed_mtrr_table_end - fixed_mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
1:
@@ -152,7 +152,7 @@ wait_for_sipi:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
xorl %eax, %eax
rep stosl
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index ba90c25c72..05d4889f3f 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -63,7 +63,7 @@ wait_for_sipi:
post_code(0x21)
/* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -119,7 +119,7 @@ clear_mtrrs:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
xorl %eax, %eax
rep stosl