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-rw-r--r--src/soc/intel/jasperlake/fsp_params.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index c45af27ece..40be0d45bf 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -349,6 +349,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
mainboard_silicon_init_params(params);
}
+/* Disable Multiphase Si init */
+int soc_fsp_multi_phase_init_is_enable(void)
+{
+ return 0;
+}
+
/* Mainboard GPIO Configuration */
__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{