diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/rockchip/rk3288/sdram.c | 14 | ||||
| -rw-r--r-- | src/soc/samsung/exynos5250/clock.c | 4 | ||||
| -rw-r--r-- | src/soc/samsung/exynos5420/clock.c | 4 |
3 files changed, 11 insertions, 11 deletions
diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 4149a4721d..e2d5537f80 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -381,8 +381,8 @@ static struct rk3288_msch_regs * const rk3288_msch[2] = { #define LP_TRIG_VAL(n) (((n) >> 4) & 7) #define PCTL_STAT_MSK (7) #define INIT_MEM (0) -#define CONFIG (1) -#define CONFIG_REQ (2) +#define CONF (1) +#define CONF_REQ (2) #define ACCESS (3) #define ACCESS_REQ (4) #define LOW_POWER (5) @@ -760,10 +760,10 @@ static void move_to_config_state(struct rk3288_ddr_publ_regs *ddr_publ_regs, case INIT_MEM: write32(&ddr_pctl_regs->sctl, CFG_STATE); while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) - != CONFIG) + != CONF) ; break; - case CONFIG: + case CONF: return; default: break; @@ -907,12 +907,12 @@ static void move_to_access_state(u32 chnum) case INIT_MEM: write32(&ddr_pctl_regs->sctl, CFG_STATE); while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) - != CONFIG) + != CONF) ; - case CONFIG: + case CONF: write32(&ddr_pctl_regs->sctl, GO_STATE); while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) - == CONFIG) + == CONF) ; break; case ACCESS: diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index a6cc3c78b9..7da7b74c53 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -22,7 +22,7 @@ #include <timer.h> /* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONF_SYS_CLK_FREQ 24000000 static struct arm_clk_ratios arm_clk_ratios[] = { { @@ -213,7 +213,7 @@ unsigned long get_pll_clk(int pllreg) /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ; + freq = CONF_SYS_CLK_FREQ; if (pllreg == EPLL) { k = k & 0xffff; diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 0da35221ed..6d9258502d 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -22,7 +22,7 @@ #include <timer.h> /* input clock of PLL: SMDK5420 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONF_SYS_CLK_FREQ 24000000 /* Epll Clock division values to achieve different frequency output */ static struct st_epll_con_val epll_div[] = { @@ -96,7 +96,7 @@ unsigned long get_pll_clk(int pllreg) /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ; + freq = CONF_SYS_CLK_FREQ; if (pllreg == EPLL || pllreg == RPLL) { k = k & 0xffff; |