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-rw-r--r--src/soc/amd/common/agesawrapper.h1
-rw-r--r--src/soc/amd/stoneyridge/Makefile.inc3
-rw-r--r--src/soc/amd/stoneyridge/bootblock/bootblock.c23
-rw-r--r--src/soc/amd/stoneyridge/fixme.c79
-rw-r--r--src/soc/amd/stoneyridge/northbridge.c34
5 files changed, 57 insertions, 83 deletions
diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h
index b42f531352..3b925b2426 100644
--- a/src/soc/amd/common/agesawrapper.h
+++ b/src/soc/amd/common/agesawrapper.h
@@ -51,7 +51,6 @@ AGESA_STATUS agesawrapper_fchs3laterestore(void);
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
VOID amd_initcpuio(void);
-VOID amd_initmmio(void);
const void *agesawrapper_locate_module(const CHAR8 name[8]);
void OemPostParams(AMD_POST_PARAMS *PostParams);
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 78ece2ef91..85452c4350 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -39,7 +39,6 @@ subdirs-y += ../../../cpu/x86/smm
bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
bootblock-y += BiosCallOuts.c
-bootblock-y += fixme.c
bootblock-y += bootblock/bootblock.c
bootblock-y += early_setup.c
bootblock-y += pmutil.c
@@ -50,7 +49,6 @@ romstage-y += romstage.c
romstage-y += early_setup.c
romstage-y += dimmSpd.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
-romstage-y += fixme.c
romstage-y += gpio.c
romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
romstage-y += pmutil.c
@@ -73,7 +71,6 @@ ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
-ramstage-y += fixme.c
ramstage-y += gpio.c
ramstage-y += hda.c
ramstage-y += southbridge.c
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 1712b5159a..461f32dbff 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -17,6 +17,9 @@
#include <stdint.h>
#include <assert.h>
#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/amdfam15.h>
#include <smp/node.h>
#include <bootblock_common.h>
#include <agesawrapper.h>
@@ -37,6 +40,26 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
bootblock_main_with_timestamp(base_timestamp);
}
+/* Set the MMIO Configuration Base Address and Bus Range. */
+static void amd_initmmio(void)
+{
+ msr_t mmconf;
+ msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+ int mtrr;
+
+ mmconf.hi = 0;
+ mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
+ | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
+ wrmsr(MMIO_CONF_BASE, mmconf);
+
+ /*
+ * todo: AGESA currently writes variable MTRRs. Once that is
+ * corrected, un-hardcode this MTRR.
+ */
+ mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;
+ set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+}
+
void bootblock_soc_early_init(void)
{
amd_initmmio();
diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c
deleted file mode 100644
index 67517250fd..0000000000
--- a/src/soc/amd/stoneyridge/fixme.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/lapic_def.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdfam15.h>
-#include <soc/pci_devs.h>
-#include <soc/pci_devs.h>
-#include <soc/northbridge.h>
-#include <soc/southbridge.h>
-#include <agesawrapper.h>
-
-/*
- * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,
- * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining
- * MMIO to posted. Route all I/O to the southbridge.
- */
-void amd_initcpuio(void)
-{
- msr_t topmem = rdmsr(TOP_MEM); /* todo: build bsp_topmem() earlier */
- uintptr_t base, limit;
-
- /* Enable legacy video routing: D18F1xF4 VGA Enable */
- pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
-
- /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
- base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
- limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;
- pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit);
- pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base);
-
- /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
- base = (topmem.lo >> 8) | MMIO_WE | MMIO_RE;
- limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8;
- pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit);
- pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base);
-
- /* Route all I/O downstream */
- base = 0 | IO_WE | IO_RE;
- limit = ALIGN_DOWN(0xffff, 4 * KiB);
- pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit);
- pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base);
-}
-
-/* Set the MMIO Configuration Base Address and Bus Range. */
-void amd_initmmio(void)
-{
- msr_t mmconf;
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- int mtrr;
-
- mmconf.hi = 0;
- mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
- | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
- wrmsr(MMIO_CONF_BASE, mmconf);
-
- /*
- * todo: AGESA currently writes variable MTRRs. Once that is
- * corrected, un-hardcode this MTRR.
- */
- mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;
- set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
-}
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index dfe4724c96..3eb8e8dfe1 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -23,6 +23,7 @@
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam15.h>
#include <cpu/cpu.h>
+#include <cpu/x86/lapic_def.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci.h>
@@ -30,6 +31,7 @@
#include <agesawrapper.h>
#include <agesawrapper_call.h>
#include <soc/northbridge.h>
+#include <soc/southbridge.h>
#include <soc/pci_devs.h>
#include <stdint.h>
#include <stdlib.h>
@@ -335,6 +337,38 @@ static const struct pci_driver family15_northbridge __pci_driver = {
.device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT,
};
+/*
+ * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,
+ * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining
+ * MMIO to posted. Route all I/O to the southbridge.
+ */
+void amd_initcpuio(void)
+{
+ uintptr_t topmem = bsp_topmem();
+ uintptr_t base, limit;
+
+ /* Enable legacy video routing: D18F1xF4 VGA Enable */
+ pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
+
+ /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
+ base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
+ limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;
+ pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit);
+ pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base);
+
+ /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
+ base = (topmem >> 8) | MMIO_WE | MMIO_RE;
+ limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8;
+ pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit);
+ pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base);
+
+ /* Route all I/O downstream */
+ base = 0 | IO_WE | IO_RE;
+ limit = ALIGN_DOWN(0xffff, 4 * KiB);
+ pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit);
+ pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base);
+}
+
void fam15_finalize(void *chip_info)
{
device_t dev;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 10:57:06 +0000