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-rw-r--r--src/soc/nvidia/tegra132/Kconfig1
-rw-r--r--src/soc/nvidia/tegra132/Makefile.inc1
-rw-r--r--src/soc/nvidia/tegra132/cpu_lib.S23
-rw-r--r--src/soc/nvidia/tegra132/soc.c21
-rw-r--r--src/soc/nvidia/tegra210/Makefile.inc1
-rw-r--r--src/soc/nvidia/tegra210/cpu_lib.S23
-rw-r--r--src/soc/nvidia/tegra210/soc.c26
7 files changed, 4 insertions, 92 deletions
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index 4420e52e7c..cb6798c8ac 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -12,7 +12,6 @@ config SOC_NVIDIA_TEGRA132
select HAVE_HARD_RESET
select HAVE_UART_SPECIAL
select ARM_BOOTBLOCK_CUSTOM
- select SMP
select GENERIC_GPIO_LIB
select HAS_PRECBMEM_TIMESTAMP_REGION
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 592c34f30a..22ccba5626 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -61,7 +61,6 @@ ramstage-y += 32bit_reset.S
ramstage-y += addressmap.c
ramstage-y += cbmem.c
ramstage-y += cpu.c
-ramstage-y += cpu_lib.S
ramstage-y += clock.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += dc.c
ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += dsi.c
diff --git a/src/soc/nvidia/tegra132/cpu_lib.S b/src/soc/nvidia/tegra132/cpu_lib.S
deleted file mode 100644
index 90406433ff..0000000000
--- a/src/soc/nvidia/tegra132/cpu_lib.S
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-.text
-.global smp_processor_id
-smp_processor_id:
- /* Core 0 and 1 are encoded in the Aff0 (7:0) field of MPIDR_EL1. */
- mrs x0, mpidr_el1
- uxtb w0, w0
- ret
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 99896bef77..8eabd39f2e 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -55,25 +55,6 @@ static void soc_read_resources(device_t dev)
ram_resource(dev, index++, begin * KiB, size * KiB);
}
-static size_t cntrl_total_cpus(void)
-{
- return CONFIG_MAX_CPUS;
-}
-
-static int cntrl_start_cpu(unsigned int id, void (*entry)(void))
-{
- if (id != 1)
- return -1;
- start_cpu(1, entry);
- return 0;
-}
-
-static struct cpu_control_ops cntrl_ops = {
- .total_cpus = cntrl_total_cpus,
- .start_cpu = cntrl_start_cpu,
-};
-
-
static void lock_down_vpr(void)
{
struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE;
@@ -87,7 +68,7 @@ static void soc_init(device_t dev)
{
clock_init_arm_generic_timer();
- arch_initialize_cpus(dev, &cntrl_ops);
+ arch_initialize_cpu(dev);
/* Lock down VPR */
lock_down_vpr();
diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc
index 2898cec780..84d59d7721 100644
--- a/src/soc/nvidia/tegra210/Makefile.inc
+++ b/src/soc/nvidia/tegra210/Makefile.inc
@@ -64,7 +64,6 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-y += addressmap.c
ramstage-y += cbmem.c
ramstage-y += cpu.c
-ramstage-y += cpu_lib.S
ramstage-y += clock.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += dc.c
ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += dsi.c
diff --git a/src/soc/nvidia/tegra210/cpu_lib.S b/src/soc/nvidia/tegra210/cpu_lib.S
deleted file mode 100644
index 90406433ff..0000000000
--- a/src/soc/nvidia/tegra210/cpu_lib.S
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-.text
-.global smp_processor_id
-smp_processor_id:
- /* Core 0 and 1 are encoded in the Aff0 (7:0) field of MPIDR_EL1. */
- mrs x0, mpidr_el1
- uxtb w0, w0
- ret
diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c
index 871c148946..bcbef49d10 100644
--- a/src/soc/nvidia/tegra210/soc.c
+++ b/src/soc/nvidia/tegra210/soc.c
@@ -58,30 +58,11 @@ static void soc_read_resources(device_t dev)
ram_resource(dev, index++, begin * KiB, size * KiB);
}
-static size_t cntrl_total_cpus(void)
-{
- return CONFIG_MAX_CPUS;
-}
-
-static int cntrl_start_cpu(unsigned int id, void (*entry)(void))
-{
- if (id >= CONFIG_MAX_CPUS)
- return -1;
- start_cpu(id, entry);
- return 0;
-}
-
-static struct cpu_control_ops cntrl_ops = {
- .total_cpus = cntrl_total_cpus,
- .start_cpu = cntrl_start_cpu,
-};
-
-
static void soc_init(device_t dev)
{
clock_init_arm_generic_timer();
- arch_initialize_cpus(dev, &cntrl_ops);
+ arch_initialize_cpu(dev);
if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
return;
@@ -132,9 +113,8 @@ struct chip_operations soc_nvidia_tegra210_ops = {
static void tegra210_cpu_init(device_t cpu)
{
- if (cpu_is_bsp())
- if (tegra210_run_mtc() != 0)
- printk(BIOS_ERR, "MTC: No training data.\n");
+ if (tegra210_run_mtc() != 0)
+ printk(BIOS_ERR, "MTC: No training data.\n");
}
static const struct cpu_device_id ids[] = {