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-rw-r--r--src/soc/intel/skylake/acpi.c6
-rw-r--r--src/soc/intel/skylake/flash_controller.c5
-rw-r--r--src/soc/intel/skylake/gpio.c6
-rw-r--r--src/soc/intel/skylake/igd.c2
-rw-r--r--src/soc/intel/skylake/lpc.c9
-rw-r--r--src/soc/intel/skylake/systemagent.c2
6 files changed, 18 insertions, 12 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 4892656b89..c01066f7fb 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -573,11 +573,15 @@ void southcluster_inject_dsdt(device_t device)
/* Save wake source information for calculating ACPI _SWS values */
int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
{
- struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+ struct chipset_power_state *ps;
static uint32_t gpe0_sts[GPE0_REG_MAX];
uint32_t pm1_en;
int i;
+ ps = cbmem_find(CBMEM_ID_POWER_STATE);
+ if (ps == NULL)
+ return -1;
+
/* PM1_EN state is lost in Deep S3 so enable basic wake events */
pm1_en = ps->pm1_en | PCIEXPWAK_STS | RTC_STS | PWRBTN_STS | BM_STS;
*pm1 = ps->pm1_sts & pm1_en;
diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index aca22a9cea..25562a5e9a 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -191,11 +191,6 @@ int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
}
flash->spi->rw = SPI_WRITE_FLAG;
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
- return ret;
- }
start = offset;
end = start + len;
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 64b3dda334..db4b8c3ce6 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -261,6 +261,9 @@ static void gpio_handle_pad_mode(const struct pad_config *cfg)
bit = 0;
hostsw_own_reg = gpio_hostsw_reg(cfg->pad, &bit);
+ if (hostsw_own_reg == NULL)
+ return;
+
reg = read32(hostsw_own_reg);
reg &= ~(1U << bit);
@@ -282,7 +285,8 @@ static void gpi_enable_smi(gpio_t pad)
uint32_t pad_mask;
comm = gpio_get_community(pad);
-
+ if (comm == NULL)
+ return;
regs = pcr_port_regs(comm->port_id);
gpi_status_reg = (void *)&regs[GPI_SMI_STS_OFFSET];
gpi_en_reg = (void *)&regs[GPI_SMI_EN_OFFSET];
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 9268c095f5..b87467f4a5 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -118,7 +118,7 @@ static int init_igd_opregion(igd_opregion_t *opregion)
die("vbt data not found");
memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
- sizeof(IGD_OPREGION_SIGNATURE));
+ sizeof(IGD_OPREGION_SIGNATURE) - 1);
memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32));
memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index ff413f49ba..e47026c4f8 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -209,9 +209,12 @@ static inline int pch_io_range_in_default(u16 base, u16 size)
if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
return 0;
- /* Is it entirely contained? */
- if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
- (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
+ /*
+ * Is it entirely contained?
+ * Since LPC_DEFAULT_IO_RANGE_LOWER is Zero,
+ * it need not be checked against lower base.
+ */
+ if ((base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
return 1;
/* This will return not in range for partial overlaps. */
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index ff65731e98..ed02f44092 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -183,7 +183,7 @@ static void read_map_entry(device_t dev, struct map_entry *entry,
value <<= 32;
}
- value |= pci_read_config32(dev, entry->reg);
+ value |= (uint64_t) pci_read_config32(dev, entry->reg);
value &= mask;
if (entry->is_limit)