summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/alderlake/fsp_params.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index a21ca4a1b5..6de8649cb8 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
+#include <cbfs.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -89,6 +90,8 @@ __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
+ const struct microcode *microcode_file;
+ size_t microcode_len;
FSP_S_CONFIG *params = &supd->FspsConfig;
struct device *dev;
@@ -99,6 +102,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Parse device tree and enable/disable Serial I/O devices */
parse_devicetree(params);
+ microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len);
+
+ if ((microcode_file != NULL) && (microcode_len != 0)) {
+ /* Update CPU Microcode patch base address/size */
+ params->MicrocodeRegionBase = (uint32_t)microcode_file;
+ params->MicrocodeRegionSize = (uint32_t)microcode_len;
+ }
+
/* Load VBT before devicetree-specific config. */
params->GraphicsConfigPtr = (uintptr_t)vbt_get();