2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 87d4eb0707..1c3ec792ae 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -169,6 +169,9 @@ static int get_cores_per_package(void)
 
 void acpi_init_gnvs(global_nvs_t *gnvs)
 {
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct soc_intel_skylake_config *config = dev->chip_info;
+
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
@@ -189,6 +192,9 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 #endif
 	gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
 #endif
+
+	/* Enable DPTF based on mainboard configuration */
+	gnvs->dpte = config->dptf_enable;
 }
 
 unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 9b43b7fa2d..94aa3a4ea9 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -86,6 +86,9 @@ struct soc_intel_skylake_config {
 	/* Enable S0iX support */
 	int s0ix_enable;
 
+	/* Enable DPTF support */
+	int dptf_enable;
+
 	/* Deep SX enable for both AC and DC */
 	int deep_s3_enable;
 	int deep_s5_enable;