6 files changed, 18 insertions, 5 deletions

diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index dae64cc420..22b5ce4be0 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -67,6 +67,9 @@ asmlinkage void car_stage_entry(void)
 	if (romstage_handoff_init(s3_resume))
 		printk(BIOS_ERR, "Failed to set romstage handoff data\n");
 
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
 	post_code(0x44);
 	if (postcar_frame_init(&pcf, 1 * KiB))
 		die("Unable to initialize postcar frame.\n");
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 42b08338d4..4cadc68a89 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -152,6 +152,9 @@ asmlinkage void car_stage_entry(void)
 	if (romstage_handoff_init(s3_resume))
 		printk(BIOS_ERR, "Failed to set romstage handoff data\n");
 
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
 	post_code(0x44);
 	if (postcar_frame_init(&pcf, 0))
 		die("Unable to initialize postcar frame.\n");
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 8361bb1972..6bf8aac9af 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #if CONFIG(EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #endif
@@ -146,6 +147,9 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
 	/* Call into mainboard. */
 	mainboard_romstage_entry(&rp);
 
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
 	prepare_and_run_postcar(&early_mtrrs);
 	/* We do not return here. */
 }
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 523d1f56f4..44c2392abc 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -15,10 +15,6 @@ source "src/soc/intel/common/pch/Kconfig"
 comment "Intel SoC Common coreboot stages"
 source "src/soc/intel/common/basecode/Kconfig"
 
-config DISPLAY_SMM_MEMORY_MAP
-	bool "SMM: Display the SMM memory map"
-	default n
-
 config SOC_INTEL_COMMON_RESET
 	bool
 	default n
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 52f4dc9d63..35b531a465 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -24,6 +24,7 @@
 #include <console/usb.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
@@ -255,9 +256,11 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
 
 	romstage_handoff_init(prev_sleep_state == ACPI_S3);
 
-	post_code(0x4f);
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
 
 	/* Load the ramstage. */
+	post_code(0x4f);
 	run_ramstage();
 	while (1);
 }
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 3b74a1cb69..1f71c98283 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <console/usb.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <timestamp.h>
 #include <version.h>
@@ -169,6 +170,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
 	if (!CONFIG(FSP_MEMORY_DOWN))
 		save_dimm_info();
 
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
 	/* Load the ramstage. */
 	post_code(0x4e);
 	run_ramstage();