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-rw-r--r--src/soc/intel/apollolake/chip.h12
-rw-r--r--src/soc/intel/apollolake/memmap.c21
-rw-r--r--src/soc/intel/apollolake/romstage.c20
3 files changed, 52 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 882e481fd7..396f607245 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -121,6 +121,18 @@ struct soc_intel_apollolake_config {
/* GPIO SD card detect pin */
unsigned int sdcard_cd_gpio;
+
+ /* PRMRR size setting with three options
+ * 0x02000000 - 32MiB
+ * 0x04000000 - 64MiB
+ * 0x08000000 - 128MiB */
+ uint32_t PrmrrSize;
+
+ /* Enable SGX feature.
+ * Enabling SGX feature is 2 step process,
+ * (1) set sgx_enable = 1
+ * (2) set PrmrrSize to supported size */
+ uint8_t sgx_enable;
};
typedef struct soc_intel_apollolake_config config_t;
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index f9a484a7c4..6d68501162 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -26,6 +26,7 @@
#include <arch/io.h>
#include <assert.h>
#include <cbmem.h>
+#include "chip.h"
#include <device/pci.h>
#include <fsp/memmap.h>
#include <intelblocks/smm.h>
@@ -34,7 +35,25 @@
void *cbmem_top(void)
{
- return (void *)sa_get_tseg_base();
+ const struct device *dev;
+ const config_t *config;
+ void *tolum = (void *)sa_get_tseg_base();
+
+ if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+ return tolum;
+
+ dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ assert(dev != NULL);
+ config = dev->chip_info;
+
+ if (!config)
+ die("Failed to get chip_info\n");
+
+ /* FSP allocates 2x PRMRR Size Memory for alignment */
+ if (config->sgx_enable)
+ tolum -= config->PrmrrSize * 2;
+
+ return tolum;
}
int smm_subregion(int sub, void **start, size_t *size)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 605a75b523..cc02ff5db0 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -320,6 +320,22 @@ static void check_full_retrain(const FSPM_UPD *mupd)
}
}
+static void soc_memory_init_params(FSPM_UPD *mupd)
+{
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+ /* Only for GLK */
+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ assert(dev != NULL);
+ const config_t *config = dev->chip_info;
+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+ if (!config)
+ die("Can not find SoC devicetree\n");
+
+ m_cfg->PrmrrSize = config->PrmrrSize;
+#endif
+}
+
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
struct region_device rdev;
@@ -327,6 +343,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
check_full_retrain(mupd);
fill_console_params(mupd);
+
+ if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+ soc_memory_init_params(mupd);
+
mainboard_memory_init_params(mupd);
/* Do NOT let FSP do any GPIO pad configuration */