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-rw-r--r--src/soc/intel/apollolake/cpu.c2
-rw-r--r--src/soc/intel/cannonlake/cpu.c2
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c5
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cpulib.h2
-rw-r--r--src/soc/intel/skylake/cpu.c2
5 files changed, 7 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 9337eb3417..690589443c 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -73,7 +73,7 @@ void soc_core_init(struct device *cpu)
/* TODO(adurbin): This should only be done on a cold boot. Also, some
* of these banks are core vs package scope. For now every CPU clears
* every bank. */
- mca_configure();
+ mca_configure(NULL);
/* Set core MSRs */
reg_script_run(core_msr_script);
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index dc413e2df1..ba87045555 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -172,7 +172,7 @@ void soc_core_init(struct device *cpu)
/* TODO(adurbin): This should only be done on a cold boot. Also, some
* of these banks are core vs package scope. For now every CPU clears
* every bank. */
- mca_configure();
+ mca_configure(NULL);
/* Enable the local CPU apics */
enable_lapic_tpr();
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index c67904f198..112a0496a0 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -297,7 +297,7 @@ uint32_t cpu_get_max_turbo_ratio(void)
return msr.lo & 0xff;
}
-void mca_configure(void)
+void mca_configure(void *unused)
{
msr_t msr;
int i;
@@ -306,6 +306,7 @@ void mca_configure(void)
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & 0xff;
msr.lo = msr.hi = 0;
+
for (i = 0; i < num_banks; i++) {
/* Clear the machine check status */
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index 191459be5f..88f04b439a 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -157,6 +157,6 @@ uint32_t cpu_get_power_max(void);
uint32_t cpu_get_max_turbo_ratio(void);
/* Configure Machine Check Architecture support */
-void mca_configure(void);
+void mca_configure(void *unused);
#endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 3a499ce1e7..5535ec641d 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -425,7 +425,7 @@ void soc_core_init(struct device *cpu)
/* TODO(adurbin): This should only be done on a cold boot. Also, some
* of these banks are core vs package scope. For now every CPU clears
* every bank. */
- mca_configure();
+ mca_configure(NULL);
/* Enable the local CPU apics */
enable_lapic_tpr();