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-rw-r--r--src/soc/intel/cannonlake/Kconfig1
-rw-r--r--src/soc/intel/cannonlake/include/soc/pmc.h2
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 36fa59615b..259a4a04d3 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -87,6 +87,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
+ select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CNVI
select SOC_INTEL_COMMON_BLOCK_CPU
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index 3576d80969..7b00398a36 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -103,6 +103,8 @@
#define GPE0_DWX_MASK 0xf
#define GPE0_DW_SHIFT(x) (4*(x))
+#define SLP_S0_RES 0x193c
+
#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
/*
* The values for GPIO_CFG in Intel Document #572235 are incorrect.