diff options
Diffstat (limited to 'src/soc/samsung/exynos5420')
| -rw-r--r-- | src/soc/samsung/exynos5420/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 3c4bb04794..04125d9cb1 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -582,7 +582,7 @@ int clock_epll_set_rate(unsigned long rate) epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; /* - * Required period ( in cycles) to generate a stable clock output. + * Required period (in cycles) to generate a stable clock output. * The maximum clock time can be up to 3000 * PDIV cycles of PLLs * frequency input (as per spec) */ |