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Diffstat (limited to 'src/soc/samsung/exynos5250')
-rw-r--r--src/soc/samsung/exynos5250/fb.c1
-rw-r--r--src/soc/samsung/exynos5250/i2c.c6
-rw-r--r--src/soc/samsung/exynos5250/include/soc/dsim.h1
-rw-r--r--src/soc/samsung/exynos5250/include/soc/setup.h1
4 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c
index 98a4c663ec..9166b02cad 100644
--- a/src/soc/samsung/exynos5250/fb.c
+++ b/src/soc/samsung/exynos5250/fb.c
@@ -508,7 +508,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device)
return ret;
}
-
base = dp->base;
/* Enable enhanced mode */
setbits32(&base->sys_ctl_4, ENHANCED);
diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c
index 5a6226df95..bc5570daad 100644
--- a/src/soc/samsung/exynos5250/i2c.c
+++ b/src/soc/samsung/exynos5250/i2c.c
@@ -94,9 +94,6 @@ static struct s3c24x0_i2c_bus i2c_busses[] = {
},
};
-
-
-
static int i2c_int_pending(struct i2c_regs *regs)
{
return read8(&regs->con) & I2cConIntPending;
@@ -146,9 +143,6 @@ static int i2c_wait_for_int(struct i2c_regs *regs)
return 1;
}
-
-
-
static int i2c_send_stop(struct i2c_regs *regs)
{
uint8_t mode = read8(&regs->stat) & (I2cStatModeMask);
diff --git a/src/soc/samsung/exynos5250/include/soc/dsim.h b/src/soc/samsung/exynos5250/include/soc/dsim.h
index 8aba3f5ac5..d85180252b 100644
--- a/src/soc/samsung/exynos5250/include/soc/dsim.h
+++ b/src/soc/samsung/exynos5250/include/soc/dsim.h
@@ -52,7 +52,6 @@ check_member(exynos5_dsim, phyacchr1, 0x54);
#define VIDEO_MODE (1 << 25)
#define BURST_MODE (1 << 26)
-
#define DSIM_PHYACCHR_AFC_EN (1 << 14)
#define DSIM_PHYACCHR_AFC_CTL_OFFSET 5
diff --git a/src/soc/samsung/exynos5250/include/soc/setup.h b/src/soc/samsung/exynos5250/include/soc/setup.h
index eb23eeff12..4b468cb4fa 100644
--- a/src/soc/samsung/exynos5250/include/soc/setup.h
+++ b/src/soc/samsung/exynos5250/include/soc/setup.h
@@ -141,7 +141,6 @@ struct exynos5_phy_control;
| (CPUD_RATIO << 4) \
| (ARM_RATIO))
-
/* CLK_FSYS */
#define CLK_SRC_FSYS0_VAL 0x66666
#define CLK_DIV_FSYS0_VAL 0x0BB00000