diff options
Diffstat (limited to 'src/soc/samsung/exynos5250/usb.c')
| -rw-r--r-- | src/soc/samsung/exynos5250/usb.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c index 076e42eee9..12b658aef3 100644 --- a/src/soc/samsung/exynos5250/usb.c +++ b/src/soc/samsung/exynos5250/usb.c @@ -25,9 +25,9 @@ static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) { - setbits_le32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ - setbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ - setbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ + setbits32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ } void reset_usb_drd_dwc3() @@ -77,7 +77,7 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) /* Set all PHY registers to default values */ /* XHCI Version 1.0, Frame Length adjustment 30 MHz */ - setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); + setbits32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */ write32(&phy->utmi, 1 << 6); @@ -120,13 +120,13 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) write32(&phy->resume, 0x0); udelay(10); - clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ + clrbits32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ } void setup_usb_drd_phy() { printk(BIOS_DEBUG, "Powering up USB DRD PHY\n"); - setbits_le32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN); setup_drd_phy(exynos_usb_drd_phy); } @@ -134,8 +134,8 @@ void setup_usb_host_phy(int hsic_gpio) { unsigned int hostphy_ctrl0; - setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); - setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); + setbits32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n", hsic_gpio ? "with" : "without"); @@ -156,13 +156,13 @@ void setup_usb_host_phy(int hsic_gpio) HOST_CTRL0_UTMISWRST); write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0); udelay(10); - clrbits_le32(&exynos_usb_host_phy->usbphyctrl0, - HOST_CTRL0_LINKSWRST | - HOST_CTRL0_UTMISWRST); + clrbits32(&exynos_usb_host_phy->usbphyctrl0, + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); udelay(20); /* EHCI Ctrl setting */ - setbits_le32(&exynos_usb_host_phy->ehcictrl, + setbits32(&exynos_usb_host_phy->ehcictrl, EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4 | EHCICTRL_ENAINCR8 | @@ -175,15 +175,15 @@ void setup_usb_host_phy(int hsic_gpio) gpio_direction_output(hsic_gpio, 1); udelay(5000); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_SIDDQ | - HOST_CTRL0_FORCESLEEP | - HOST_CTRL0_FORCESUSPEND); - setbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESLEEP | + HOST_CTRL0_FORCESUSPEND); + setbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); udelay(10); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); } /* At this point we need to wait for 50ms before talking to |