1 files changed, 96 insertions, 96 deletions

diff --git a/src/soc/samsung/exynos5250/dp-reg.c b/src/soc/samsung/exynos5250/dp-reg.c
index a2c0aa482d..75dadba022 100644
--- a/src/soc/samsung/exynos5250/dp-reg.c
+++ b/src/soc/samsung/exynos5250/dp-reg.c
@@ -35,7 +35,7 @@ void s5p_dp_reset(struct s5p_dp_device *dp)
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	writel(RESET_DP_TX, &base->dp_tx_sw_reset);
+	write32(&base->dp_tx_sw_reset, RESET_DP_TX);
 
 	/* Stop Video */
 	clrbits_le32(&base->video_ctl_1, VIDEO_EN);
@@ -44,73 +44,73 @@ void s5p_dp_reset(struct s5p_dp_device *dp)
 	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-	writel(reg, &base->func_en_1);
+	write32(&base->func_en_1, reg);
 
 	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 		SERDES_FIFO_FUNC_EN_N |
 		LS_CLK_DOMAIN_FUNC_EN_N;
-	writel(reg, &base->func_en_2);
+	write32(&base->func_en_2, reg);
 
 	udelay(20);
 
 	reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
 		LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
 
-	writel(reg, &base->lane_map);
+	write32(&base->lane_map, reg);
 
-	writel(0x0, &base->sys_ctl_1);
-	writel(0x40, &base->sys_ctl_2);
-	writel(0x0, &base->sys_ctl_3);
-	writel(0x0, &base->sys_ctl_4);
+	write32(&base->sys_ctl_1, 0x0);
+	write32(&base->sys_ctl_2, 0x40);
+	write32(&base->sys_ctl_3, 0x0);
+	write32(&base->sys_ctl_4, 0x0);
 
-	writel(0x0, &base->pkt_send_ctl);
-	writel(0x0, &base->dp_hdcp_ctl);
+	write32(&base->pkt_send_ctl, 0x0);
+	write32(&base->dp_hdcp_ctl, 0x0);
 
-	writel(0x5e, &base->dp_hpd_deglitch_l);
-	writel(0x1a, &base->dp_hpd_deglitch_h);
+	write32(&base->dp_hpd_deglitch_l, 0x5e);
+	write32(&base->dp_hpd_deglitch_h, 0x1a);
 
-	writel(0x10, &base->dp_debug_ctl);
+	write32(&base->dp_debug_ctl, 0x10);
 
-	writel(0x0, &base->dp_phy_test);
+	write32(&base->dp_phy_test, 0x0);
 
-	writel(0x0, &base->dp_video_fifo_thrd);
-	writel(0x20, &base->dp_audio_margin);
+	write32(&base->dp_video_fifo_thrd, 0x0);
+	write32(&base->dp_audio_margin, 0x20);
 
-	writel(0x4, &base->m_vid_gen_filter_th);
-	writel(0x2, &base->m_aud_gen_filter_th);
+	write32(&base->m_vid_gen_filter_th, 0x4);
+	write32(&base->m_aud_gen_filter_th, 0x2);
 
-	writel(0x00000101, &base->soc_general_ctl);
+	write32(&base->soc_general_ctl, 0x00000101);
 
 	/* Set Analog Parameters */
-	writel(0x10, &base->analog_ctl_1);
-	writel(0x0C, &base->analog_ctl_2);
-	writel(0x85, &base->analog_ctl_3);
-	writel(0x66, &base->pll_filter_ctl_1);
-	writel(0x0, &base->tx_amp_tuning_ctl);
+	write32(&base->analog_ctl_1, 0x10);
+	write32(&base->analog_ctl_2, 0x0C);
+	write32(&base->analog_ctl_3, 0x85);
+	write32(&base->pll_filter_ctl_1, 0x66);
+	write32(&base->tx_amp_tuning_ctl, 0x0);
 
 	/* Set interrupt pin assertion polarity as high */
-	writel(INT_POL0 | INT_POL1, &base->int_ctl);
+	write32(&base->int_ctl, INT_POL0 | INT_POL1);
 
 	/* Clear pending registers */
-	writel(0xff, &base->common_int_sta_1);
-	writel(0x4f, &base->common_int_sta_2);
-	writel(0xe0, &base->common_int_sta_3);
-	writel(0xe7, &base->common_int_sta_4);
-	writel(0x63, &base->dp_int_sta);
+	write32(&base->common_int_sta_1, 0xff);
+	write32(&base->common_int_sta_2, 0x4f);
+	write32(&base->common_int_sta_3, 0xe0);
+	write32(&base->common_int_sta_4, 0xe7);
+	write32(&base->dp_int_sta, 0x63);
 
 	/* 0:mask,1: unmask */
-	writel(0x00, &base->common_int_mask_1);
-	writel(0x00, &base->common_int_mask_2);
-	writel(0x00, &base->common_int_mask_3);
-	writel(0x00, &base->common_int_mask_4);
-	writel(0x00, &base->int_sta_mask);
+	write32(&base->common_int_mask_1, 0x00);
+	write32(&base->common_int_mask_2, 0x00);
+	write32(&base->common_int_mask_3, 0x00);
+	write32(&base->common_int_mask_4, 0x00);
+	write32(&base->int_sta_mask, 0x00);
 }
 
 unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(&dp->base->dp_debug_ctl);
+	reg = read32(&dp->base->dp_debug_ctl);
 	if (reg & PLL_LOCK)
 		return PLL_LOCKED;
 	else
@@ -123,10 +123,10 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp)
 	struct stopwatch sw;
 	struct exynos5_dp *base = dp->base;
 
-	writel(0x00, &base->dp_phy_pd);
+	write32(&base->dp_phy_pd, 0x00);
 
 	reg = PLL_LOCK_CHG;
-	writel(reg, &base->common_int_sta_1);
+	write32(&base->common_int_sta_1, reg);
 
 	clrbits_le32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL));
 
@@ -159,7 +159,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp)
 
 	/* Clear interrupts related to AUX channel */
 	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, &base->dp_int_sta);
+	write32(&base->dp_int_sta, reg);
 
 	/* Disable AUX channel module */
 	setbits_le32(&base->func_en_2, AUX_FUNC_EN_N);
@@ -168,12 +168,12 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp)
 	reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT;
 	reg |= (0 & AUX_HW_RETRY_COUNT_MASK) << AUX_HW_RETRY_COUNT_SHIFT;
 	reg |= (AUX_HW_RETRY_INTERVAL_600_US << AUX_HW_RETRY_INTERVAL_SHIFT);
-	writel(reg, &base->aux_hw_retry_ctl) ;
+	write32(&base->aux_hw_retry_ctl, reg);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 	reg = DEFER_CTRL_EN;
 	reg |= (1 & DEFER_COUNT_MASK) << DEFER_COUNT_SHIFT;
-	writel(reg, &base->aux_ch_defer_dtl);
+	write32(&base->aux_ch_defer_dtl, reg);
 
 	/* Enable AUX channel module */
 	clrbits_le32(&base->func_en_2, AUX_FUNC_EN_N);
@@ -188,24 +188,24 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
 	setbits_le32(&base->aux_ch_ctl_2, AUX_EN);
 
 	/* Is AUX CH command reply received? */
-	reg = readl(&base->dp_int_sta);
+	reg = read32(&base->dp_int_sta);
 	while (!(reg & RPLY_RECEIV))
-		reg = readl(&base->dp_int_sta);
+		reg = read32(&base->dp_int_sta);
 
 	/* Clear interrupt source for AUX CH command reply */
-	writel(RPLY_RECEIV, &base->dp_int_sta);
+	write32(&base->dp_int_sta, RPLY_RECEIV);
 
 	/* Clear interrupt source for AUX CH access error */
-	reg = readl(&base->dp_int_sta);
+	reg = read32(&base->dp_int_sta);
 	if (reg & AUX_ERR) {
 		printk(BIOS_ERR, "%s: AUX_ERR encountered, dp_int_sta: "
 				"0x%02x\n", __func__, reg);
-		writel(AUX_ERR, &base->dp_int_sta);
+		write32(&base->dp_int_sta, AUX_ERR);
 		return -1;
 	}
 
 	/* Check AUX CH error access status */
-	reg = readl(&base->dp_int_sta);
+	reg = read32(&base->dp_int_sta);
 	if ((reg & AUX_STATUS_MASK) != 0) {
 		printk(BIOS_ERR, "AUX CH error happens: %d\n\n",
 			reg & AUX_STATUS_MASK);
@@ -226,22 +226,22 @@ int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp,
 
 	for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) {
 		/* Clear AUX CH data buffer */
-		writel(BUF_CLR, &base->buf_data_ctl);
+		write32(&base->buf_data_ctl, BUF_CLR);
 
 		/* Select DPCD device address */
 		reg = reg_addr >> AUX_ADDR_7_0_SHIFT;
 		reg &= AUX_ADDR_7_0_MASK;
-		writel(reg, &base->aux_addr_7_0);
+		write32(&base->aux_addr_7_0, reg);
 		reg = reg_addr >> AUX_ADDR_15_8_SHIFT;
 		reg &= AUX_ADDR_15_8_MASK;
-		writel(reg, &base->aux_addr_15_8);
+		write32(&base->aux_addr_15_8, reg);
 		reg = reg_addr >> AUX_ADDR_19_16_SHIFT;
 		reg &= AUX_ADDR_19_16_MASK;
-		writel(reg, &base->aux_addr_19_16);
+		write32(&base->aux_addr_19_16, reg);
 
 		/* Write data buffer */
 		reg = (unsigned int)data;
-		writel(reg, &base->buf_data_0);
+		write32(&base->buf_data_0, reg);
 
 		/*
 		 * Set DisplayPort transaction and write 1 byte
@@ -249,7 +249,7 @@ int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp,
 		 * If Bit 3 is 0, I2C transaction.
 		 */
 		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-		writel(reg, &base->aux_ch_ctl_1);
+		write32(&base->aux_ch_ctl_1, reg);
 
 		/* Start AUX transaction */
 		retval = s5p_dp_start_aux_transaction(dp);
@@ -273,18 +273,18 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
 
 	for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) {
 		/* Clear AUX CH data buffer */
-		writel(BUF_CLR, &base->buf_data_ctl);
+		write32(&base->buf_data_ctl, BUF_CLR);
 
 		/* Select DPCD device address */
 		reg = reg_addr >> AUX_ADDR_7_0_SHIFT;
 		reg &= AUX_ADDR_7_0_MASK;
-		writel(reg, &base->aux_addr_7_0);
+		write32(&base->aux_addr_7_0, reg);
 		reg = reg_addr >> AUX_ADDR_15_8_SHIFT;
 		reg &= AUX_ADDR_15_8_MASK;
-		writel(reg, &base->aux_addr_15_8);
+		write32(&base->aux_addr_15_8, reg);
 		reg = reg_addr >> AUX_ADDR_19_16_SHIFT;
 		reg &= AUX_ADDR_19_16_MASK;
-		writel(reg, &base->aux_addr_19_16);
+		write32(&base->aux_addr_19_16, reg);
 
 		/*
 		 * Set DisplayPort transaction and read 1 byte
@@ -292,7 +292,7 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
 		 * If Bit 3 is 0, I2C transaction.
 		 */
 		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-		writel(reg, &base->aux_ch_ctl_1);
+		write32(&base->aux_ch_ctl_1, reg);
 
 		/* Start AUX transaction */
 		retval = s5p_dp_start_aux_transaction(dp);
@@ -304,7 +304,7 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
 
 	/* Read data buffer */
 	if (!retval) {
-		reg = readl(&base->buf_data_0);
+		reg = read32(&base->buf_data_0);
 		*data = (unsigned char)(reg & 0xff);
 	}
 
@@ -317,17 +317,17 @@ void s5p_dp_init_video(struct s5p_dp_device *dp)
 	struct exynos5_dp *base = dp->base;
 
 	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, &base->common_int_sta_1);
+	write32(&base->common_int_sta_1, reg);
 
 	reg = 0x0;
-	writel(reg, &base->sys_ctl_1);
+	write32(&base->sys_ctl_1, reg);
 
 	reg = (4 & CHA_CRI_MASK) << CHA_CRI_SHIFT;
 	reg |= CHA_CTRL;
-	writel(reg, &base->sys_ctl_2);
+	write32(&base->sys_ctl_2, reg);
 
 	reg = 0x0;
-	writel(reg, &base->sys_ctl_3);
+	write32(&base->sys_ctl_3, reg);
 }
 
 void s5p_dp_set_video_color_format(struct s5p_dp_device *dp,
@@ -343,16 +343,16 @@ void s5p_dp_set_video_color_format(struct s5p_dp_device *dp,
 	reg = (dynamic_range << IN_D_RANGE_SHIFT) |
 		(color_depth << IN_BPC_SHIFT) |
 		(color_space << IN_COLOR_F_SHIFT);
-	writel(reg, &base->video_ctl_2);
+	write32(&base->video_ctl_2, reg);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(&base->video_ctl_3);
+	reg = read32(&base->video_ctl_3);
 	reg &= ~IN_YC_COEFFI_MASK;
 	if (coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, &base->video_ctl_3);
+	write32(&base->video_ctl_3, reg);
 }
 
 int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
@@ -360,18 +360,18 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	reg = readl(&base->sys_ctl_1);
-	writel(reg, &base->sys_ctl_1);
+	reg = read32(&base->sys_ctl_1);
+	write32(&base->sys_ctl_1, reg);
 
-	reg = readl(&base->sys_ctl_1);
+	reg = read32(&base->sys_ctl_1);
 
 	if (!(reg & DET_STA))
 		return -1;
 
-	reg = readl(&base->sys_ctl_2);
-	writel(reg, &base->sys_ctl_2);
+	reg = read32(&base->sys_ctl_2);
+	write32(&base->sys_ctl_2, reg);
 
-	reg = readl(&base->sys_ctl_2);
+	reg = read32(&base->sys_ctl_2);
 
 	if (reg & CHA_STA) {
 		printk(BIOS_DEBUG, "Input stream clk is changing\n");
@@ -393,28 +393,28 @@ void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp,
 		setbits_le32(&base->sys_ctl_4, FIX_M_VID);
 
 		reg = m_value >> M_VID_0_VALUE_SHIFT;
-		writel(reg, &base->m_vid_0);
+		write32(&base->m_vid_0, reg);
 
 		reg = (m_value >> M_VID_1_VALUE_SHIFT);
-		writel(reg, &base->m_vid_1);
+		write32(&base->m_vid_1, reg);
 
 		reg = (m_value >> M_VID_2_VALUE_SHIFT);
-		writel(reg, &base->m_vid_2);
+		write32(&base->m_vid_2, reg);
 
 		reg = n_value >> N_VID_0_VALUE_SHIFT;
-		writel(reg, &base->n_vid_0);
+		write32(&base->n_vid_0, reg);
 
 		reg = (n_value >> N_VID_1_VALUE_SHIFT);
-		writel(reg, &base->n_vid_1);
+		write32(&base->n_vid_1, reg);
 
 		reg = (n_value >> N_VID_2_VALUE_SHIFT);
-		writel(reg, &base->n_vid_2);
+		write32(&base->n_vid_2, reg);
 	} else  {
 		clrbits_le32(&base->sys_ctl_4, FIX_M_VID);
 
-		writel(0x00, &base->n_vid_0);
-		writel(0x80, &base->n_vid_1);
-		writel(0x00, &base->n_vid_2);
+		write32(&base->n_vid_0, 0x00);
+		write32(&base->n_vid_1, 0x80);
+		write32(&base->n_vid_2, 0x00);
 	}
 }
 
@@ -423,10 +423,10 @@ void s5p_dp_enable_video_master(struct s5p_dp_device *dp)
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	reg = readl(&base->soc_general_ctl);
+	reg = read32(&base->soc_general_ctl);
 	reg &= ~VIDEO_MODE_MASK;
 	reg |= VIDEO_MODE_SLAVE_MODE;
-	writel(reg, &base->soc_general_ctl);
+	write32(&base->soc_general_ctl, reg);
 }
 
 int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp)
@@ -439,10 +439,10 @@ int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp)
 	stopwatch_init_msecs_expire(&sw, STREAM_ON_TIMEOUT);
 
 	do {
-		reg = readl(&base->common_int_sta_1);
+		reg = read32(&base->common_int_sta_1);
 		if (reg & VSYNC_DET) {
 			i++;
-			writel(reg | VSYNC_DET, &base->common_int_sta_1);
+			write32(&base->common_int_sta_1, reg | VSYNC_DET);
 		}
 		if (i == 4)
 			break;
@@ -462,28 +462,28 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp,
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	reg = readl(&base->func_en_1);
+	reg = read32(&base->func_en_1);
 	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, &base->func_en_1);
+	write32(&base->func_en_1, reg);
 
-	reg = readl(&base->video_ctl_10);
+	reg = read32(&base->video_ctl_10);
 	reg &= ~INTERACE_SCAN_CFG;
 	reg |= (video_info->interlaced << 2);
-	writel(reg, &base->video_ctl_10);
+	write32(&base->video_ctl_10, reg);
 
-	reg = readl(&base->video_ctl_10);
+	reg = read32(&base->video_ctl_10);
 	reg &= ~VSYNC_POLARITY_CFG;
 	reg |= (video_info->v_sync_polarity << 1);
-	writel(reg, &base->video_ctl_10);
+	write32(&base->video_ctl_10, reg);
 
-	reg = readl(&base->video_ctl_10);
+	reg = read32(&base->video_ctl_10);
 	reg &= ~HSYNC_POLARITY_CFG;
 	reg |= (video_info->h_sync_polarity << 0);
-	writel(reg, &base->video_ctl_10);
+	write32(&base->video_ctl_10, reg);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, &base->soc_general_ctl);
+	write32(&base->soc_general_ctl, reg);
 }
 
 void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp)
@@ -491,7 +491,7 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp)
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	reg = readl(&base->dp_hw_link_training);
+	reg = read32(&base->dp_hw_link_training);
 	while (reg & HW_TRAINING_EN)
-		reg = readl(&base->dp_hw_link_training);
+		reg = read32(&base->dp_hw_link_training);
 }