diff options
Diffstat (limited to 'src/soc/samsung/exynos5250/dmc_init_ddr3.c')
| -rw-r--r-- | src/soc/samsung/exynos5250/dmc_init_ddr3.c | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c index 029171efdc..f4150203ea 100644 --- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c @@ -19,20 +19,6 @@ static void reset_phy_ctrl(void) write32(&exynos_clock->lpddr3phy_ctrl, LPDDR3PHY_CTRL_PHY_RESET_DISABLE); -#if 0 - /* - * For proper memory initialization there should be a minimum delay of - * 500us after the LPDDR3PHY_CTRL_PHY_RESET signal. - * The below value is an approximate value whose calculation in done - * considering that sdelay takes 2 instruction for every 1 delay cycle. - * And assuming each instruction takes 1 clock cycle i.e 1/(1.7 Ghz)sec - * So for 500 usec, the number of delay cycle should be - * (500 * 10^-6) * (1.7 * 10^9) / 2 = 425000 - * - * TODO(hatim.rv@samsung.com): Implement the delay using timer/counter - */ - sdelay(425000); -#endif udelay(500); } |