diff options
Diffstat (limited to 'src/soc/rockchip')
| -rw-r--r-- | src/soc/rockchip/rk3288/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/bootblock.c | 2 | ||||
| -rwxr-xr-x | src/soc/rockchip/rk3288/clock.c | 265 | ||||
| -rwxr-xr-x | src/soc/rockchip/rk3288/clock.h | 29 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/cpu.h | 26 | ||||
| -rwxr-xr-x | src/soc/rockchip/rk3288/grf.h | 103 |
6 files changed, 428 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 50a1bbfcf6..13c811475b 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -25,15 +25,18 @@ bootblock-y += media.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif +bootblock-y += clock.c romstage-y += cbmem.c romstage-y += timer.c romstage-y += monotonic_timer.c romstage-y += media.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += clock.c ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += monotonic_timer.c +ramstage-y += clock.c ramstage-y += media.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index 9adf6ac242..04afae5529 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -21,8 +21,10 @@ #include <arch/cache.h> #include <bootblock_common.h> #include "timer.h" +#include "clock.h" static void bootblock_cpu_init(void) { rk3288_init_timer(); + rkclk_init(); } diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c new file mode 100755 index 0000000000..3087a1377f --- /dev/null +++ b/src/soc/rockchip/rk3288/clock.c @@ -0,0 +1,265 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <assert.h> +#include <stdlib.h> +#include <arch/io.h> +#include <stdint.h> +#include <console/console.h> +#include <delay.h> +#include "clock.h" +#include "grf.h" +#include "addressmap.h" +#include "cpu.h" + +struct pll_div { + u32 nr; + u32 nf; + u32 no; +}; + +struct rk3288_cru_reg { + u32 cru_apll_con[4]; + u32 cru_dpll_con[4]; + u32 cru_cpll_con[4]; + u32 cru_gpll_con[4]; + u32 cru_npll_con[4]; + u32 cru_mode_con; + u32 reserved0[3]; + u32 cru_clksel_con[43]; + u32 reserved1[21]; + u32 cru_clkgate_con[19]; + u32 reserved2; + u32 cru_glb_srst_fst_value; + u32 cru_glb_srst_snd_value; + u32 cru_softrst_con[12]; + u32 cru_misc_con; + u32 cru_glb_cnt_th; + u32 cru_glb_rst_con; + u32 reserved3; + u32 cru_glb_rst_st; + u32 reserved4; + u32 cru_sdmmc_con[2]; + u32 cru_sdio0_con[2]; + u32 cru_sdio1_con[2]; + u32 cru_emmc_con[2]; +}; +check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c); + +static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; + +/* apll = 816MHz, gpll = 594MHz, cpll = 384MHz, dpll = 300MHz */ +static const struct pll_div apll_init_cfg = {.nr = 1, .nf = 68, .no = 2}; +static const struct pll_div gpll_init_cfg = {.nr = 2, .nf = 198, .no = 4}; +static const struct pll_div cpll_init_cfg = {.nr = 2, .nf = 128, .no = 4}; +static const struct pll_div dpll_init_cfg = {.nr = 1, .nf = 50, .no = 4}; + +/*******************PLL CON0 BITS***************************/ +#define PLL_OD_MSK (0x0F) + +#define PLL_NR_MSK (0x3F << 8) +#define PLL_NR_SHIFT (8) + +/*******************PLL CON1 BITS***************************/ +#define PLL_NF_MSK (0x1FFF) + +/*******************PLL CON2 BITS***************************/ +#define PLL_BWADJ_MSK (0x0FFF) + +/*******************PLL CON3 BITS***************************/ +#define PLL_RESET_MSK (1 << 5) +#define PLL_RESET (1 << 5) +#define PLL_RESET_RESUME (0 << 5) + +/*******************CLKSEL0 BITS***************************/ +/* core clk pll sel: amr or general */ +#define CORE_SEL_PLL_MSK (1 << 15) +#define CORE_SEL_APLL (0 << 15) +#define CORE_SEL_GPLL (1 << 15) + +/* a12 core clock div: clk_core = clk_src / (div_con + 1) */ +#define A12_DIV_SHIFT (8) +#define A12_DIV_MSK (0x1F << 8) + +/* mp core axi clock div: clk = clk_src / (div_con + 1) */ +#define MP_DIV_SHIFT (4) +#define MP_DIV_MSK (0xF << 4) + +/* m0 core axi clock div: clk = clk_src / (div_con + 1) */ +#define M0_DIV_MSK (0xF) + +/*******************CLKSEL10 BITS***************************/ +/* peripheral bus clk pll sel: codec or general */ +#define PERI_SEL_PLL_MSK (1 << 15) +#define PERI_SEL_CPLL (0 << 15) +#define PERI_SEL_GPLL (1 << 15) + +/* peripheral bus pclk div: + * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 + */ +#define PERI_PCLK_DIV_SHIFT (12) +#define PERI_PCLK_DIV_MSK (0x7 << 12) + +/* peripheral bus hclk div: + * aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 + */ +#define PERI_HCLK_DIV_SHIFT (8) +#define PERI_HCLK_DIV_MSK (0x3 << 8) + +/* peripheral bus aclk div: + * aclk_periph = + * periph_clk_src / (peri_aclk_div_con + 1) + */ +#define PERI_ACLK_DIV_MSK (0x1F) + +/*******************CLKSEL37 BITS***************************/ +#define L2_DIV_MSK (0x7) + +#define ATCLK_DIV_MSK (0x1F << 4) +#define ATCLK_DIV_SHIFT (4) + +#define PCLK_DBG_DIV_MSK (0x1F << 9) +#define PCLK_DBG_DIV_SHIFT (9) + +#define APLL_MODE_MSK (0x3) +#define APLL_MODE_SLOW (0) +#define APLL_MODE_NORM (1) + +#define DPLL_MODE_MSK (0x3 << 4) +#define DPLL_MODE_SLOW (0 << 4) +#define DPLL_MODE_NORM (1 << 4) + +#define CPLL_MODE_MSK (0x3 << 8) +#define CPLL_MODE_SLOW (0 << 8) +#define CPLL_MODE_NORM (1 << 8) + +#define GPLL_MODE_MSK (0x3 << 12) +#define GPLL_MODE_SLOW (0 << 12) +#define GPLL_MODE_NORM (1 << 12) + +#define SOCSTS_DPLL_LOCK (1 << 5) +#define SOCSTS_APLL_LOCK (1 << 6) +#define SOCSTS_CPLL_LOCK (1 << 7) +#define SOCSTS_GPLL_LOCK (1 << 8) + +static int rkclk_set_pll(u32 *pll_con, const struct pll_div *pll_div_cfg) +{ + /* enter rest */ + writel(RK_SETBITS(PLL_RESET, PLL_RESET_MSK), &pll_con[3]); + + writel(RK_SETBITS((pll_div_cfg->nr - 1) << PLL_NR_SHIFT, PLL_NR_MSK) + | RK_SETBITS((pll_div_cfg->no - 1), PLL_OD_MSK), &pll_con[0]); + + writel(RK_SETBITS((pll_div_cfg->nf - 1), PLL_NF_MSK), + &pll_con[1]); + + writel(RK_SETBITS(((pll_div_cfg->nf >> 1) - 1), PLL_BWADJ_MSK), + &pll_con[2]); + + udelay(10); + + /* return form rest */ + writel(RK_SETBITS(PLL_RESET_RESUME, PLL_RESET_MSK), &pll_con[3]); + + return 0; +} + +void rkclk_init(void) +{ + /* pll enter slow-mode */ + writel(RK_SETBITS(APLL_MODE_SLOW, APLL_MODE_MSK) + | RK_SETBITS(GPLL_MODE_SLOW, GPLL_MODE_MSK) + | RK_SETBITS(CPLL_MODE_SLOW, CPLL_MODE_MSK) + | RK_SETBITS(DPLL_MODE_SLOW, DPLL_MODE_MSK), + &cru_ptr->cru_mode_con); + + /* init pll */ + rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg); + rkclk_set_pll(&cru_ptr->cru_gpll_con[0], &gpll_init_cfg); + rkclk_set_pll(&cru_ptr->cru_cpll_con[0], &cpll_init_cfg); + rkclk_set_pll(&cru_ptr->cru_dpll_con[0], &dpll_init_cfg); + + /* waiting for pll lock */ + while (1) { + if ((readl(&rk3288_grf->soc_status[1]) + & (SOCSTS_APLL_LOCK | SOCSTS_CPLL_LOCK + | SOCSTS_DPLL_LOCK | SOCSTS_GPLL_LOCK)) + == (SOCSTS_APLL_LOCK | SOCSTS_CPLL_LOCK + | SOCSTS_GPLL_LOCK | SOCSTS_DPLL_LOCK)) + break; + udelay(1); + } + + /* + * core clock pll source selection and + * set up dependent divisors for MPAXI/M0AXI and ARM clocks. + * core clock select apll, apll clk = 816MHz + * arm clk = 816MHz, mpclk = 204MHz, m0clk = 408MHz + */ + writel(RK_SETBITS(CORE_SEL_APLL, CORE_SEL_PLL_MSK) + | RK_SETBITS(0 << A12_DIV_SHIFT, A12_DIV_MSK) + | RK_SETBITS(3 << MP_DIV_SHIFT, MP_DIV_MSK) + | RK_SETBITS(1, M0_DIV_MSK), + &cru_ptr->cru_clksel_con[0]); + + /* + * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. + * l2ramclk = 408MHz, atclk = 204MHz, pclk_dbg = 204MHz + */ + writel(RK_SETBITS(1, L2_DIV_MSK) + | RK_SETBITS((3 << ATCLK_DIV_SHIFT), ATCLK_DIV_MSK) + | RK_SETBITS((3 << PCLK_DBG_DIV_SHIFT), PCLK_DBG_DIV_MSK), + &cru_ptr->cru_clksel_con[37]); + + /* + * peri clock pll source selection and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + * peri clock select gpll, gpll clk = 594MHz + * aclk = 148.5MHz, hclk = 148.5Mhz, pclk = 74.25MHz + */ + writel(RK_SETBITS(PERI_SEL_GPLL, PERI_SEL_PLL_MSK) + | RK_SETBITS(1 << PERI_PCLK_DIV_SHIFT, PERI_PCLK_DIV_MSK) + | RK_SETBITS(0 << PERI_HCLK_DIV_SHIFT, PERI_HCLK_DIV_MSK) + | RK_SETBITS(3, PERI_ACLK_DIV_MSK), + &cru_ptr->cru_clksel_con[10]); + + /* PLL enter normal-mode */ + writel(RK_SETBITS(APLL_MODE_NORM, APLL_MODE_MSK) + | RK_SETBITS(GPLL_MODE_NORM, GPLL_MODE_MSK) + | RK_SETBITS(CPLL_MODE_NORM, CPLL_MODE_MSK) + | RK_SETBITS(DPLL_MODE_NORM, DPLL_MODE_MSK), + &cru_ptr->cru_mode_con); + +} + +void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy) +{ + u32 phy_ctl_srstn_shift = 4 + 5 * ch; + u32 ctl_psrstn_shift = 3 + 5 * ch; + u32 ctl_srstn_shift = 2 + 5 * ch; + u32 phy_psrstn_shift = 1 + 5 * ch; + u32 phy_srstn_shift = 5 * ch; + + writel(RK_SETBITS(phy << phy_ctl_srstn_shift, 1 << phy_ctl_srstn_shift) + | RK_SETBITS(ctl << ctl_psrstn_shift, 1 << ctl_psrstn_shift) + | RK_SETBITS(ctl << ctl_srstn_shift, 1 << ctl_srstn_shift) + | RK_SETBITS(phy << phy_psrstn_shift, 1 << phy_psrstn_shift) + | RK_SETBITS(phy << phy_srstn_shift, 1 << phy_srstn_shift), + &cru_ptr->cru_softrst_con[10]); +} diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h new file mode 100755 index 0000000000..cc2ec78d16 --- /dev/null +++ b/src/soc/rockchip/rk3288/clock.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_CLOCK_H__ +#define __SOC_ROCKCHIP_RK3288_CLOCK_H__ + +#include "addressmap.h" + +void rkclk_init(void); +void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); + +#endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ + diff --git a/src/soc/rockchip/rk3288/cpu.h b/src/soc/rockchip/rk3288/cpu.h new file mode 100644 index 0000000000..ed629c975f --- /dev/null +++ b/src/soc/rockchip/rk3288/cpu.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_CPU_H__ +#define __SOC_ROCKCHIP_RK3288_CPU_H__ + +#define RK_SETBITS(val, msk) (((msk) << 16) | (val)) + +#endif /* __SOC_ROCKCHIP_RK3288_CPU_H__ */ + diff --git a/src/soc/rockchip/rk3288/grf.h b/src/soc/rockchip/rk3288/grf.h new file mode 100755 index 0000000000..4b99f4b6bf --- /dev/null +++ b/src/soc/rockchip/rk3288/grf.h @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_GRF_H__ +#define __SOC_ROCKCHIP_RK3288_GRF_H__ +#include "addressmap.h" + +struct rk3288_grf_gpio_lh { + u32 gpiol; + u32 gpioh; +}; + +struct rk3288_grf_gpio_pe { + u32 gpioa; + u32 gpiob; + u32 gpioc; + u32 gpiod; +}; + +struct rk3288_grf_regs { + u32 reserved[3]; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 reserved2; + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3dl_iomux; + u32 gpio3dh_iomux; + u32 gpio4al_iomux; + u32 gpio4ah_iomux; + u32 gpio4bl_iomux; + u32 reserved3; + u32 gpio4c_iomux; + u32 gpio4d_iomux; + u32 reserved4; + u32 gpio5b_iomux; + u32 gpio5c_iomux; + u32 gpio6a_iomux; + u32 reserved5; + u32 gpio6b_iomux; + u32 gpio6c_iomux; + u32 reserved6; + u32 gpio7a_iomux; + u32 gpio7b_iomux; + u32 gpio7cl_iomux; + u32 gpio7ch_iomux; + u32 reserved7; + u32 gpio8a_iomux; + u32 gpio8b_iomux; + u32 reserved8[30]; + struct rk3288_grf_gpio_lh gpio_sr[8]; + struct rk3288_grf_gpio_pe gpio_p[8]; + struct rk3288_grf_gpio_pe gpio_e[8]; + u32 gpio_smt; + u32 soc_con[15]; + u32 soc_status[22]; + u32 reserved9[2]; + u32 peridmac_con[4]; + u32 ddrc0_con0; + u32 ddrc1_con0; + u32 cpu_con[5]; + u32 reserved10[3]; + u32 cpu_status0; + u32 reserved11; + u32 uoc0_con[5]; + u32 uoc1_con[5]; + u32 uoc2_con[4]; + u32 uoc3_con[2]; + u32 uoc4_con[2]; + u32 pvtm_con[3]; + u32 pvtm_status[3]; + u32 io_vsel; + u32 saradc_testbit; + u32 tsadc_testbit_l; + u32 tsadc_testbit_h; + u32 os_reg[4]; + u32 reserved12; + u32 soc_con15; + u32 soc_con16; +}; +check_member(rk3288_grf_regs, soc_con16, 0x3a8); + +static struct rk3288_grf_regs * const rk3288_grf = (void *)GRF_BASE; +#endif |